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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-11-07 15:20:32 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-11-07 15:20:32 +0000 |
| commit | 59ab8afb46d74604f438d78213a641c038c519b8 (patch) | |
| tree | 1f212c51c36da749e2ab9de978a9b8fc4b896e5a | |
| parent | ece4180609c6ec2e21dfef5f27eb9bf7b65351e4 (diff) | |
| download | external_llvm-59ab8afb46d74604f438d78213a641c038c519b8.zip external_llvm-59ab8afb46d74604f438d78213a641c038c519b8.tar.gz external_llvm-59ab8afb46d74604f438d78213a641c038c519b8.tar.bz2 | |
It turns out that the testcase in question uncovered subreg-handling bug.
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86375 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp | 1 | ||||
| -rw-r--r-- | test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll | 1 |
3 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp index a3f52cd..c130ced 100644 --- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp @@ -347,9 +347,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, &ARM::DPR_VFP2RegClass); O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']'; } else { - if (unsigned SubReg = MO.getSubReg()) - Reg = TRI->getSubReg(Reg, SubReg); - + assert(!MO.getSubReg() && "Subregs should be eliminated!"); O << getRegisterName(Reg); } break; diff --git a/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp b/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp index 8686961..c49fee3 100644 --- a/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp @@ -137,6 +137,7 @@ void ARMMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { case MachineOperand::MO_Register: // Ignore all implicit register operands. if (MO.isImplicit()) continue; + assert(!MO.getSubReg() && "Subregs should be eliminated!"); MCOp = MCOperand::CreateReg(MO.getReg()); break; case MachineOperand::MO_Immediate: diff --git a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll index 0a06991..fe177c3 100644 --- a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll +++ b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll @@ -1,4 +1,5 @@ ; RUN: llc -mcpu=cortex-a8 < %s | FileCheck %s +; XFAIL: * target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "armv7-eabi" |