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| author | Jack Carter <jcarter@mips.com> | 2012-08-07 00:35:22 +0000 |
|---|---|---|
| committer | Jack Carter <jcarter@mips.com> | 2012-08-07 00:35:22 +0000 |
| commit | 5b0e9ce2e54726a4b6e2a5008764fe67f3b79c88 (patch) | |
| tree | 8f1037e0fbca7b45373d68418b6d58e7b506c5db | |
| parent | 121418e55191904b01eb9ec182ef62af5f38e861 (diff) | |
| download | external_llvm-5b0e9ce2e54726a4b6e2a5008764fe67f3b79c88.zip external_llvm-5b0e9ce2e54726a4b6e2a5008764fe67f3b79c88.tar.gz external_llvm-5b0e9ce2e54726a4b6e2a5008764fe67f3b79c88.tar.bz2 | |
The define for 64 bit sign extension neglected to
initialize fields of the class that it used.
The result was nonsense code.
Before:
0000000000000000 <foo>:
0: 00441100 0x441100
4: 03e00008 jr ra
8: 00000000 nop
After:
0000000000000000 <foo>:
0: 00041000 sll v0,a0,0x0
4: 03e00008 jr ra
8: 00000000 nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161377 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 15 | ||||
| -rw-r--r-- | test/MC/Mips/sext_64_32.ll | 15 |
2 files changed, 23 insertions, 7 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 952c8b0..5bebc4f 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -219,13 +219,14 @@ def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>; def DEXT : ExtBase<3, "dext", CPU64Regs>; def DINS : InsBase<7, "dins", CPU64Regs>; -def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), - "dsll\t$rd, $rt, 32", [], IIAlu>; -def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), - "sll\t$rd, $rt, 0", [], IIAlu>; -let isCodeGenOnly = 1 in -def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), - "sll\t$rd, $rt, 0", [], IIAlu>; +let isCodeGenOnly = 1, rs = 0, shamt = 0 in { + def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), + "dsll\t$rd, $rt, 32", [], IIAlu>; + def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), + "sll\t$rd, $rt, 0", [], IIAlu>; + def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), + "sll\t$rd, $rt, 0", [], IIAlu>; +} } //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions diff --git a/test/MC/Mips/sext_64_32.ll b/test/MC/Mips/sext_64_32.ll new file mode 100644 index 0000000..bc0b5b1 --- /dev/null +++ b/test/MC/Mips/sext_64_32.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | llvm-objdump -disassemble -triple mips64el - | FileCheck %s + +; Sign extend from 32 to 64 was creating nonsense opcodes + +; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, 0 + +; ModuleID = '../sext.c' +;target datalayout = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v64:64:64-n32" +;target triple = "mips64el-unknown-linux" + +define i64 @foo(i32 %ival) nounwind readnone { +entry: + %conv = sext i32 %ival to i64 + ret i64 %conv +} |