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authorChris Lattner <sabre@nondot.org>2008-08-26 06:07:47 +0000
committerChris Lattner <sabre@nondot.org>2008-08-26 06:07:47 +0000
commit5fedcd4d0cd4188dfcbd3c5513d0c3f5d8013798 (patch)
tree23b5a07091747a8c38b7452cf336300312967d44
parent0b08b15eca3e5893384df86a140260d68d2205f5 (diff)
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typo fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55355 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 7ec5b85..f35c8d8 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -4231,7 +4231,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
if (!SawEarlyClobber &&
OpInfo.Type == InlineAsm::isClobber &&
OpInfo.ConstraintType == TargetLowering::C_Register) {
- // Note that we want to ignore things that we don't trick here, like
+ // Note that we want to ignore things that we don't track here, like
// dirflag, fpsr, flags, etc.
std::pair<unsigned, const TargetRegisterClass*> PhysReg =
TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,