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| author | Lauro Ramos Venancio <lauro.venancio@gmail.com> | 2007-02-23 20:32:57 +0000 |
|---|---|---|
| committer | Lauro Ramos Venancio <lauro.venancio@gmail.com> | 2007-02-23 20:32:57 +0000 |
| commit | 600c383e5c96d4b107b3e6ed4515eac25246cb02 (patch) | |
| tree | b2a83da14af6ef126095f9b967f7a7c657cf2c21 | |
| parent | cae0a193e310050b6bb9cc4628b7151997126f60 (diff) | |
| download | external_llvm-600c383e5c96d4b107b3e6ed4515eac25246cb02.zip external_llvm-600c383e5c96d4b107b3e6ed4515eac25246cb02.tar.gz external_llvm-600c383e5c96d4b107b3e6ed4515eac25246cb02.tar.bz2 | |
Fix stack alignment in functions with varargs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34532 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 7 | ||||
| -rw-r--r-- | test/CodeGen/ARM/vargs_align.ll | 20 |
2 files changed, 25 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 90d02b8..f573198 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -831,13 +831,16 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { SSARegMap *RegMap = MF.getSSARegMap(); MachineFrameInfo *MFI = MF.getFrameInfo(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); - unsigned VARegSaveSize = (4 - NumGPRs) * 4; + unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned VARegSize = (4 - NumGPRs) * 4; + unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); if (VARegSaveSize) { // If this function is vararg, store any remaining integer argument regs // to their spots on the stack so that they may be loaded by deferencing // the result of va_next. AFI->setVarArgsRegSaveSize(VARegSaveSize); - VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset); + VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset + + VARegSaveSize - VARegSize); SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); SmallVector<SDOperand, 4> MemOps; diff --git a/test/CodeGen/ARM/vargs_align.ll b/test/CodeGen/ARM/vargs_align.ll new file mode 100644 index 0000000..b9702e5 --- /dev/null +++ b/test/CodeGen/ARM/vargs_align.ll @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llc -march=arm && +; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnueabi -disable-fp-elim | grep "add sp, sp, #16" && +; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-linux-gnu -disable-fp-elim | grep "add sp, sp, #12" + +define i32 @f(i32 %a, ...) { +entry: + %a_addr = alloca i32 ; <i32*> [#uses=1] + %retval = alloca i32, align 4 ; <i32*> [#uses=2] + %tmp = alloca i32, align 4 ; <i32*> [#uses=2] + "alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store i32 %a, i32* %a_addr + store i32 0, i32* %tmp + %tmp1 = load i32* %tmp ; <i32> [#uses=1] + store i32 %tmp1, i32* %retval + br label %return + +return: ; preds = %entry + %retval2 = load i32* %retval ; <i32> [#uses=1] + ret i32 %retval2 +} |