diff options
| author | Benjamin Kramer <benny.kra@googlemail.com> | 2013-05-22 17:01:12 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2013-05-22 17:01:12 +0000 |
| commit | 60ef6c9295844038406c6083b67ea24b3646f2dd (patch) | |
| tree | c539a166c46559d9958ada6ca6ba02a0cd4ad2d9 | |
| parent | 6e4a9c14f6e59b075b3a24825d2dc7dc9e163281 (diff) | |
| download | external_llvm-60ef6c9295844038406c6083b67ea24b3646f2dd.zip external_llvm-60ef6c9295844038406c6083b67ea24b3646f2dd.tar.gz external_llvm-60ef6c9295844038406c6083b67ea24b3646f2dd.tar.bz2 | |
X86: When expanding PCMPGTQ to PCMPGTD we always want to compare the lower halves as unsigned.
Take #2 on fixing PR15977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182486 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 15 | ||||
| -rw-r--r-- | test/CodeGen/X86/vec_compare.ll | 14 |
2 files changed, 25 insertions, 4 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 1f35056..769f901 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -9358,12 +9358,19 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget, Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1); // Since SSE has no unsigned integer comparisons, we need to flip the sign - // bits of the inputs before performing those operations. + // bits of the inputs before performing those operations. The lower + // compare is always unsigned. + SDValue SB; if (FlipSigns) { - SDValue SB = DAG.getConstant(0x80000000U, MVT::v4i32); - Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB); - Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB); + SB = DAG.getConstant(0x80000000U, MVT::v4i32); + } else { + SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32); + SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32); + SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + Sign, Zero, Sign, Zero); } + Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB); + Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB); // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2)) SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1); diff --git a/test/CodeGen/X86/vec_compare.ll b/test/CodeGen/X86/vec_compare.ll index 9532499..fd5c234 100644 --- a/test/CodeGen/X86/vec_compare.ll +++ b/test/CodeGen/X86/vec_compare.ll @@ -67,7 +67,15 @@ define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) nounwind { } define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK: [[CONSTSEG:[A-Z0-9_]*]]: +; CHECK: .long 2147483648 +; CHECK-NEXT: .long 0 +; CHECK-NEXT: .long 2147483648 +; CHECK-NEXT: .long 0 ; CHECK: test7: +; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]] +; CHECK: pxor [[CONSTREG]] +; CHECK: pxor [[CONSTREG]] ; CHECK: pcmpgtd %xmm1 ; CHECK: pshufd $-96 ; CHECK: pcmpeqd @@ -83,6 +91,8 @@ define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind { ; CHECK: test8: +; CHECK: pxor +; CHECK: pxor ; CHECK: pcmpgtd %xmm0 ; CHECK: pshufd $-96 ; CHECK: pcmpeqd @@ -98,6 +108,8 @@ define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind { ; CHECK: test9: +; CHECK: pxor +; CHECK: pxor ; CHECK: pcmpgtd %xmm0 ; CHECK: pshufd $-96 ; CHECK: pcmpeqd @@ -115,6 +127,8 @@ define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @test10(<2 x i64> %A, <2 x i64> %B) nounwind { ; CHECK: test10: +; CHECK: pxor +; CHECK: pxor ; CHECK: pcmpgtd %xmm1 ; CHECK: pshufd $-96 ; CHECK: pcmpeqd |