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author | Nadav Rotem <nadav.rotem@intel.com> | 2012-03-15 08:49:06 +0000 |
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committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-03-15 08:49:06 +0000 |
commit | 6431ff96be8f2f7bf3428fdaa3ad4d30bf2c1db3 (patch) | |
tree | a8601a415f0a496c191a63fd191c92c77860f11e | |
parent | 8d101c31d293bcb8ece8fecdb3325cd0728bed08 (diff) | |
download | external_llvm-6431ff96be8f2f7bf3428fdaa3ad4d30bf2c1db3.zip external_llvm-6431ff96be8f2f7bf3428fdaa3ad4d30bf2c1db3.tar.gz external_llvm-6431ff96be8f2f7bf3428fdaa3ad4d30bf2c1db3.tar.bz2 |
When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, add the new node into the work list because there is a potential for further optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152784 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 | ||||
-rw-r--r-- | test/CodeGen/X86/2012-03-15-build_vector_wl.ll | 10 |
2 files changed, 14 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8337d76..32b9fa4 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -7422,6 +7422,8 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { // will be type-legalized to complex code sequences. // We perform this optimization only before the operation legalizer because we // may introduce illegal operations. + // Create a new simpler BUILD_VECTOR sequence which other optimizations can + // turn into a single shuffle instruction. if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) && ValidTypes) { bool isLE = TLI.isLittleEndian(); @@ -7462,6 +7464,8 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VecVT, &Ops[0], Ops.size()); + // The new BUILD_VECTOR node has the potential to be further optimized. + AddToWorkList(BV.getNode()); // Bitcast to the desired type. return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV); } diff --git a/test/CodeGen/X86/2012-03-15-build_vector_wl.ll b/test/CodeGen/X86/2012-03-15-build_vector_wl.ll new file mode 100644 index 0000000..fec17e9 --- /dev/null +++ b/test/CodeGen/X86/2012-03-15-build_vector_wl.ll @@ -0,0 +1,10 @@ + +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s +; CHECK: build_vector_again +define <4 x i8> @build_vector_again(<16 x i8> %in) nounwind readnone { +entry: + %out = shufflevector <16 x i8> %in, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +; CHECK: shufb + ret <4 x i8> %out +; CHECK: ret +} |