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| author | Preston Gurd <preston.gurd@intel.com> | 2012-05-01 19:50:22 +0000 |
|---|---|---|
| committer | Preston Gurd <preston.gurd@intel.com> | 2012-05-01 19:50:22 +0000 |
| commit | 66413b61f0fee8f8177aeadb27d16e8eb7d30472 (patch) | |
| tree | 3b16a87ed22323c108208470143508eb52fbb98d | |
| parent | 686c01854e49748ef2e23851bd0abfa8b9b414f3 (diff) | |
| download | external_llvm-66413b61f0fee8f8177aeadb27d16e8eb7d30472.zip external_llvm-66413b61f0fee8f8177aeadb27d16e8eb7d30472.tar.gz external_llvm-66413b61f0fee8f8177aeadb27d16e8eb7d30472.tar.bz2 | |
This patch marks the X86 floating point stack registers ST0-ST7 as reserved
in order to avoid assertion failures in the register scavenger. The assertion
failures were “Bad machine code: Using an undefined physical register” and
“Bad machine code: MBB exits via unconditional fall-through but its successor
differs from its CFG successor!”.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155930 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.cpp | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 6e00a55..402c54c 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -299,6 +299,16 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { Reserved.set(X86::FS); Reserved.set(X86::GS); + // Mark the floating point stack registers as reserved. + Reserved.set(X86::ST0); + Reserved.set(X86::ST1); + Reserved.set(X86::ST2); + Reserved.set(X86::ST3); + Reserved.set(X86::ST4); + Reserved.set(X86::ST5); + Reserved.set(X86::ST6); + Reserved.set(X86::ST7); + // Reserve the registers that only exist in 64-bit mode. if (!Is64Bit) { // These 8-bit registers are part of the x86-64 extension even though their |