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author | David Goodwin <david_goodwin@apple.com> | 2009-06-30 22:50:01 +0000 |
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committer | David Goodwin <david_goodwin@apple.com> | 2009-06-30 22:50:01 +0000 |
commit | 6647cea111ab4d83483b28712b5ba8244e6612f2 (patch) | |
tree | 6bfa617b6a818fab643654310109d71e56b4588c | |
parent | 374d8bddacbffce7c82ce81103d30b5ee42032df (diff) | |
download | external_llvm-6647cea111ab4d83483b28712b5ba8244e6612f2.zip external_llvm-6647cea111ab4d83483b28712b5ba8244e6612f2.tar.gz external_llvm-6647cea111ab4d83483b28712b5ba8244e6612f2.tar.bz2 |
Thumb-2 load and store double description. But nothing yet creates them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74566 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 27 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 14 |
2 files changed, 40 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 527659a..258adb5 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -100,6 +100,8 @@ public: SDValue &OffImm); bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base, SDValue &OffImm); + bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base, + SDValue &OffImm); bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base, SDValue &OffReg, SDValue &ShImm); @@ -613,6 +615,31 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N, return false; } +bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N, + SDValue &Base, SDValue &OffImm) { + if (N.getOpcode() == ISD::ADD) { + if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { + int RHSC = (int)RHS->getZExtValue(); + if (((RHSC & 0x3) == 0) && (RHSC < 0 && RHSC > -0x400)) { // 8 bits. + Base = N.getOperand(0); + OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); + return true; + } + } + } else if (N.getOpcode() == ISD::SUB) { + if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { + int RHSC = (int)RHS->getZExtValue(); + if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits. + Base = N.getOperand(0); + OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32); + return true; + } + } + } + + return false; +} + bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base, SDValue &OffReg, SDValue &ShImm) { diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 810cb06..2bc71f8 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -143,6 +143,13 @@ def t2addrmode_imm8 : Operand<i32>, let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); } +// t2addrmode_imm8s4 := reg + (imm8 << 2) +def t2addrmode_imm8s4 : Operand<i32>, + ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> { + let PrintMethod = "printT2AddrModeImm8Operand"; + let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); +} + // t2addrmode_so_reg := reg + reg << imm2 def t2addrmode_so_reg : Operand<i32>, ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { @@ -476,7 +483,7 @@ defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>; let mayLoad = 1 in { // Load doubleword -def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), +def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr), "ldrd", " $dst, $addr", []>; def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr), "ldrd", " $dst, $addr", []>; @@ -527,6 +534,11 @@ defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>; defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; +// Store doubleword +let mayLoad = 1 in +def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr), + "strd", " $src, $addr", []>; + //===----------------------------------------------------------------------===// // Move Instructions. // |