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author | Andrew Lenharth <andrewl@lenharth.org> | 2008-11-11 06:06:07 +0000 |
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committer | Andrew Lenharth <andrewl@lenharth.org> | 2008-11-11 06:06:07 +0000 |
commit | 683a9226532914f2ee9b7ddb9d76e7ee84079e9e (patch) | |
tree | 3e3c518f515724412dbb61fe2f3aedf2410590ef | |
parent | 00ec49b6bafc33ee17d97ec1c723e1edb41d4c97 (diff) | |
download | external_llvm-683a9226532914f2ee9b7ddb9d76e7ee84079e9e.zip external_llvm-683a9226532914f2ee9b7ddb9d76e7ee84079e9e.tar.gz external_llvm-683a9226532914f2ee9b7ddb9d76e7ee84079e9e.tar.bz2 |
fix another libgcc blocker
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59026 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Alpha/AlphaISelLowering.cpp | 1 | ||||
-rw-r--r-- | test/CodeGen/Alpha/2008-11-10-smul_lohi.ll | 22 |
2 files changed, 23 insertions, 0 deletions
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 7878830..1872b42 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -97,6 +97,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) setOperationAction(ISD::SUBE , MVT::i64, Expand); setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); + setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); // We don't support sin/cos/sqrt/pow diff --git a/test/CodeGen/Alpha/2008-11-10-smul_lohi.ll b/test/CodeGen/Alpha/2008-11-10-smul_lohi.ll new file mode 100644 index 0000000..9d814da --- /dev/null +++ b/test/CodeGen/Alpha/2008-11-10-smul_lohi.ll @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc -march=alpha + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f128:128:128" +target triple = "alphaev6-unknown-linux-gnu" + +define i64 @__mulvdi3(i64 %a, i64 %b) nounwind { +entry: + %0 = sext i64 %a to i128 ; <i128> [#uses=1] + %1 = sext i64 %b to i128 ; <i128> [#uses=1] + %2 = mul i128 %1, %0 ; <i128> [#uses=2] + %3 = lshr i128 %2, 64 ; <i128> [#uses=1] + %4 = trunc i128 %3 to i64 ; <i64> [#uses=1] + %5 = trunc i128 %2 to i64 ; <i64> [#uses=1] + %6 = icmp eq i64 %4, 0 ; <i1> [#uses=1] + br i1 %6, label %bb1, label %bb + +bb: ; preds = %entry + unreachable + +bb1: ; preds = %entry + ret i64 %5 +} |