Rename PEXTR to PEXT. Add intrinsics for BMI instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 223 insertions, 39 deletions

diff --git a/include/llvm/IntrinsicsX86.td b/include/llvm/IntrinsicsX86.td
index d445a01..db9c9ce 100644
--- a/include/llvm/IntrinsicsX86.td
+++ b/include/llvm/IntrinsicsX86.td
@@ -1629,3 +1629,37 @@ let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
               Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
                         llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
 }
+
+//===----------------------------------------------------------------------===//
+// BMI
+
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_bmi_bextr_32 : GCCBuiltin<"__builtin_ia32_bextr_u32">,
+              Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_bmi_bextr_64 : GCCBuiltin<"__builtin_ia32_bextr_u64">,
+              Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+  def int_x86_bmi_bzhi_32 : GCCBuiltin<"__builtin_ia32_bzhi_si">,
+              Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_bmi_bzhi_64 : GCCBuiltin<"__builtin_ia32_bzhi_di">,
+              Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+  def int_x86_bmi_blsi_32 :
+              Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_bmi_blsi_64 :
+              Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
+  def int_x86_bmi_blsmsk_32 :
+              Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_bmi_blsmsk_64 :
+              Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
+  def int_x86_bmi_blsr_32 :
+              Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_bmi_blsr_64 :
+              Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
+  def int_x86_bmi_pdep_32 :
+              Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_bmi_pdep_64 :
+              Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+  def int_x86_bmi_pext_32 :
+              Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_bmi_pext_64 :
+              Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+}
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index e3701ca..0994ab9 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -1401,57 +1401,80 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in {
 }
 
 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
-                   RegisterClass RC, X86MemOperand x86memop> {
+                   RegisterClass RC, X86MemOperand x86memop, Intrinsic Int,
+                   PatFrag ld_frag> {
   def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
-             !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, T8, VEX_4V;
+             !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
+             [(set RC:$dst, (Int RC:$src)), (implicit EFLAGS)]>, T8, VEX_4V;
   def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
-             !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, T8, VEX_4V;
+             !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
+             [(set RC:$dst, (Int (ld_frag addr:$src))), (implicit EFLAGS)]>,
+             T8, VEX_4V;
 }
 
 let Predicates = [HasBMI], Defs = [EFLAGS] in {
-  defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
-  defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
-  defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
-  defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
-  defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
-  defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
+  defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
+                        int_x86_bmi_blsr_32, loadi32>;
+  defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
+                        int_x86_bmi_blsr_64, loadi64>, VEX_W;
+  defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
+                          int_x86_bmi_blsmsk_32, loadi32>;
+  defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
+                          int_x86_bmi_blsmsk_64, loadi64>, VEX_W;
+  defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
+                        int_x86_bmi_blsi_32, loadi32>;
+  defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
+                        int_x86_bmi_blsi_64, loadi64>, VEX_W;
 }
 
 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
-                          X86MemOperand x86memop> {
+                          X86MemOperand x86memop, Intrinsic Int,
+                          PatFrag ld_frag> {
   def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
              !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-             []>, T8, VEX_4VOp3;
+             [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
+             T8, VEX_4VOp3;
   def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
              !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-             []>, T8, VEX_4VOp3;
+             [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
+              (implicit EFLAGS)]>, T8, VEX_4VOp3;
 }
 
 let Predicates = [HasBMI], Defs = [EFLAGS] in {
-  defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem>;
-  defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem>, VEX_W;
+  defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
+                                int_x86_bmi_bextr_32, loadi32>;
+  defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
+                                int_x86_bmi_bextr_64, loadi64>, VEX_W;
 }
 
 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
-  defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem>;
-  defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem>, VEX_W;
+  defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
+                               int_x86_bmi_bzhi_32, loadi32>;
+  defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
+                               int_x86_bmi_bzhi_64, loadi64>, VEX_W;
 }
 
-multiclass bmi_pdep_pextr<string mnemonic, RegisterClass RC,
-                          X86MemOperand x86memop> {
+multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
+                         X86MemOperand x86memop, Intrinsic Int,
+                         PatFrag ld_frag> {
   def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
              !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-             []>, VEX_4V;
+             [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
+             VEX_4V;
   def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
              !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-             []>, VEX_4V;
+             [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
 }
 
 let Predicates = [HasBMI2] in {
-  defm PDEP32 : bmi_pdep_pextr<"pdep{l}", GR32, i32mem>, T8XD;
-  defm PDEP64 : bmi_pdep_pextr<"pdep{q}", GR64, i64mem>, T8XD, VEX_W;
-  defm PEXTR32 : bmi_pdep_pextr<"pextr{l}", GR32, i32mem>, T8XS;
-  defm PEXTR64 : bmi_pdep_pextr<"pextr{q}", GR64, i64mem>, T8XS, VEX_W;
+  defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
+                               int_x86_bmi_pdep_32, loadi32>, T8XD;
+  defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
+                               int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
+  defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
+                               int_x86_bmi_pext_32, loadi32>, T8XS;
+  defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
+                               int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/test/CodeGen/X86/bmi.ll b/test/CodeGen/X86/bmi.ll
index 88c09e3..4b40d90 100644
--- a/test/CodeGen/X86/bmi.ll
+++ b/test/CodeGen/X86/bmi.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mattr=+bmi | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mattr=+bmi,+bmi2 | FileCheck %s
 
 define i32 @t1(i32 %x) nounwind  {
        %tmp = tail call i32 @llvm.cttz.i32( i32 %x )
@@ -51,3 +51,130 @@ define i64 @andn64(i64 %x, i64 %y) nounwind readnone {
 ; CHECK: andn64:
 ; CHECK: andnq
 }
+
+define i32 @bextr32(i32 %x, i32 %y) nounwind readnone {
+  %tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x, i32 %y)
+  ret i32 %tmp
+; CHECK: bextr32:
+; CHECK: bextrl
+}
+
+declare i32 @llvm.x86.bmi.bextr.32(i32, i32) nounwind readnone
+
+define i64 @bextr64(i64 %x, i64 %y) nounwind readnone {
+  %tmp = tail call i64 @llvm.x86.bmi.bextr.64(i64 %x, i64 %y)
+  ret i64 %tmp
+; CHECK: bextr64:
+; CHECK: bextrq
+}
+
+declare i64 @llvm.x86.bmi.bextr.64(i64, i64) nounwind readnone
+
+define i32 @bzhi32(i32 %x, i32 %y) nounwind readnone {
+  %tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x, i32 %y)
+  ret i32 %tmp
+; CHECK: bzhi32:
+; CHECK: bzhil
+}
+
+declare i32 @llvm.x86.bmi.bzhi.32(i32, i32) nounwind readnone
+
+define i64 @bzhi64(i64 %x, i64 %y) nounwind readnone {
+  %tmp = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %x, i64 %y)
+  ret i64 %tmp
+; CHECK: bzhi64:
+; CHECK: bzhiq
+}
+
+declare i64 @llvm.x86.bmi.bzhi.64(i64, i64) nounwind readnone
+
+define i32 @blsi32(i32 %x) nounwind readnone {
+  %tmp = tail call i32 @llvm.x86.bmi.blsi.32(i32 %x)
+  ret i32 %tmp
+; CHECK: blsi32:
+; CHECK: blsil
+}
+
+declare i32 @llvm.x86.bmi.blsi.32(i32) nounwind readnone
+
+define i64 @blsi64(i64 %x) nounwind readnone {
+  %tmp = tail call i64 @llvm.x86.bmi.blsi.64(i64 %x)
+  ret i64 %tmp
+; CHECK: blsi64:
+; CHECK: blsiq
+}
+
+declare i64 @llvm.x86.bmi.blsi.64(i64) nounwind readnone
+
+define i32 @blsmsk32(i32 %x) nounwind readnone {
+  %tmp = tail call i32 @llvm.x86.bmi.blsmsk.32(i32 %x)
+  ret i32 %tmp
+; CHECK: blsmsk32:
+; CHECK: blsmskl
+}
+
+declare i32 @llvm.x86.bmi.blsmsk.32(i32) nounwind readnone
+
+define i64 @blsmsk64(i64 %x) nounwind readnone {
+  %tmp = tail call i64 @llvm.x86.bmi.blsmsk.64(i64 %x)
+  ret i64 %tmp
+; CHECK: blsmsk64:
+; CHECK: blsmskq
+}
+
+declare i64 @llvm.x86.bmi.blsmsk.64(i64) nounwind readnone
+
+define i32 @blsr32(i32 %x) nounwind readnone {
+  %tmp = tail call i32 @llvm.x86.bmi.blsr.32(i32 %x)
+  ret i32 %tmp
+; CHECK: blsr32:
+; CHECK: blsrl
+}
+
+declare i32 @llvm.x86.bmi.blsr.32(i32) nounwind readnone
+
+define i64 @blsr64(i64 %x) nounwind readnone {
+  %tmp = tail call i64 @llvm.x86.bmi.blsr.64(i64 %x)
+  ret i64 %tmp
+; CHECK: blsr64:
+; CHECK: blsrq
+}
+
+declare i64 @llvm.x86.bmi.blsr.64(i64) nounwind readnone
+
+define i32 @pdep32(i32 %x, i32 %y) nounwind readnone {
+  %tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y)
+  ret i32 %tmp
+; CHECK: pdep32:
+; CHECK: pdepl
+}
+
+declare i32 @llvm.x86.bmi.pdep.32(i32, i32) nounwind readnone
+
+define i64 @pdep64(i64 %x, i64 %y) nounwind readnone {
+  %tmp = tail call i64 @llvm.x86.bmi.pdep.64(i64 %x, i64 %y)
+  ret i64 %tmp
+; CHECK: pdep64:
+; CHECK: pdepq
+}
+
+declare i64 @llvm.x86.bmi.pdep.64(i64, i64) nounwind readnone
+
+define i32 @pext32(i32 %x, i32 %y) nounwind readnone {
+  %tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y)
+  ret i32 %tmp
+; CHECK: pext32:
+; CHECK: pextl
+}
+
+declare i32 @llvm.x86.bmi.pext.32(i32, i32) nounwind readnone
+
+define i64 @pext64(i64 %x, i64 %y) nounwind readnone {
+  %tmp = tail call i64 @llvm.x86.bmi.pext.64(i64 %x, i64 %y)
+  ret i64 %tmp
+; CHECK: pext64:
+; CHECK: pextq
+}
+
+declare i64 @llvm.x86.bmi.pext.64(i64, i64) nounwind readnone
+
diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt
index d540bfb..37cde91 100644
--- a/test/MC/Disassembler/X86/simple-tests.txt
+++ b/test/MC/Disassembler/X86/simple-tests.txt
@@ -564,16 +564,16 @@
 # CHECK: bzhiq %r12, %r11, %r10
 0xc4 0x42 0x98 0xf5 0xd3
 
-# CHECK: pextrl %r12d, %r11d, %r10d
+# CHECK: pextl %r12d, %r11d, %r10d
 0xc4 0x42 0x22 0xf5 0xd4
 
-# CHECK: pextrl (%rax), %r11d, %r10d
+# CHECK: pextl (%rax), %r11d, %r10d
 0xc4 0x62 0x22 0xf5 0x10
 
-# CHECK: pextrq %r12, %r11, %r10
+# CHECK: pextq %r12, %r11, %r10
 0xc4 0x42 0xa2 0xf5 0xd4
 
-# CHECK: pextrq (%rax), %r11, %r10
+# CHECK: pextq (%rax), %r11, %r10
 0xc4 0x62 0xa2 0xf5 0x10
 
 # CHECK: pdepl %r12d, %r11d, %r10d
diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt
index d78232b..51901a5 100644
--- a/test/MC/Disassembler/X86/x86-32.txt
+++ b/test/MC/Disassembler/X86/x86-32.txt
@@ -520,10 +520,10 @@
 # CHECK: bzhil %esi, %ebx, %edx
 0xc4 0xe2 0x08 0xf5 0xd3
 
-# CHECK: pextrl %esp, %ecx, %edx
+# CHECK: pextl %esp, %ecx, %edx
 0xc4 0xe2 0x72 0xf5 0xd4
 
-# CHECK: pextrl (%eax), %ecx, %edx
+# CHECK: pextl (%eax), %ecx, %edx
 0xc4 0xe2 0x72 0xf5 0x10
 
 # CHECK: pdepl %esp, %ecx, %edx
diff --git a/test/MC/X86/x86_64-bmi-encoding.s b/test/MC/X86/x86_64-bmi-encoding.s
index 24acb01..005ded2 100644
--- a/test/MC/X86/x86_64-bmi-encoding.s
+++ b/test/MC/X86/x86_64-bmi-encoding.s
@@ -88,21 +88,21 @@
 // CHECK: encoding: [0xc4,0x42,0x98,0xf5,0xd3]
           bzhiq %r12, %r11, %r10
 
-// CHECK: pextrl %r12d, %r11d, %r10d
+// CHECK: pextl %r12d, %r11d, %r10d
 // CHECK: encoding: [0xc4,0x42,0x22,0xf5,0xd4]
-          pextrl %r12d, %r11d, %r10d
+          pextl %r12d, %r11d, %r10d
 
-// CHECK: pextrl (%rax), %r11d, %r10d
+// CHECK: pextl (%rax), %r11d, %r10d
 // CHECK: encoding: [0xc4,0x62,0x22,0xf5,0x10]
-          pextrl (%rax), %r11d, %r10d
+          pextl (%rax), %r11d, %r10d
 
-// CHECK: pextrq %r12, %r11, %r10
+// CHECK: pextq %r12, %r11, %r10
 // CHECK: encoding: [0xc4,0x42,0xa2,0xf5,0xd4]
-          pextrq %r12, %r11, %r10
+          pextq %r12, %r11, %r10
 
-// CHECK: pextrq (%rax), %r11, %r10
+// CHECK: pextq (%rax), %r11, %r10
 // CHECK: encoding: [0xc4,0x62,0xa2,0xf5,0x10]
-          pextrq (%rax), %r11, %r10
+          pextq (%rax), %r11, %r10
 
 // CHECK: pdepl %r12d, %r11d, %r10d
 // CHECK: encoding: [0xc4,0x42,0x23,0xf5,0xd4]