diff options
author | Bernard Ogden <bogden@arm.com> | 2013-10-14 13:16:57 +0000 |
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committer | Bernard Ogden <bogden@arm.com> | 2013-10-14 13:16:57 +0000 |
commit | 7220572e74844aa37b1b492ef67a8c1b403a254f (patch) | |
tree | cbb32269486450c5c077b7fc28707f58606a6dc5 | |
parent | 9672a89c71f7b368455ed193bc23566f3bd4ed2b (diff) | |
download | external_llvm-7220572e74844aa37b1b492ef67a8c1b403a254f.zip external_llvm-7220572e74844aa37b1b492ef67a8c1b403a254f.tar.gz external_llvm-7220572e74844aa37b1b492ef67a8c1b403a254f.tar.bz2 |
Add subtarget feature support for Cortex-A53
Some previous implicit defaults have changed, for example FP and NEON
are now on by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192590 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARM.td | 11 | ||||
-rw-r--r-- | lib/Target/ARM/ARMSubtarget.h | 2 | ||||
-rw-r--r-- | lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 9 | ||||
-rw-r--r-- | test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll | 12 | ||||
-rw-r--r-- | test/MC/ARM/invalid-fp-armv8.s | 2 | ||||
-rw-r--r-- | test/MC/ARM/invalid-neon-v8.s | 2 |
6 files changed, 28 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index f4ad3f7..9de29c1 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -196,6 +196,13 @@ def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", [FeatureT2XtPk, FeatureVFP4, FeatureAvoidPartialCPSR, FeatureTrustZone]>; + +def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", + "Cortex-A53 ARM processors", + [FeatureMP, FeatureHWDiv, FeatureHWDivARM, + FeatureTrustZone, FeatureT2XtPk, + FeatureCrypto]>; + def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", "Cortex-R5 ARM processors", [FeatureSlowFPBrcc, @@ -316,7 +323,9 @@ def : ProcessorModel<"swift", SwiftModel, FeatureHasRAS, FeatureAClass]>; // V8 Processors -def : ProcNoItin<"cortex-a53", [HasV8Ops, FeatureAClass]>; +def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass, + FeatureDB, FeatureFPARMv8, + FeatureNEON, FeatureDSPThumb2]>; //===----------------------------------------------------------------------===// // Register File Description diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index f00feac..5dc5975 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -31,7 +31,7 @@ class TargetOptions; class ARMSubtarget : public ARMGenSubtargetInfo { protected: enum ARMProcFamilyEnum { - Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift + Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift, CortexA53 }; enum ARMProcClassEnum { None, AClass, RClass, MClass diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index dc388ec..16021a2 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -103,8 +103,13 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) { if (Idx) { unsigned SubVer = TT[Idx]; if (SubVer == '8') { - // FIXME: Parse v8 features - ARMArchFeature = "+v8,+db"; + if (NoCPU) + // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2, FeatureMP, + // FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone, FeatureT2XtPk, FeatureCrypto + ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,+trustzone,+t2xtpk,+crypto"; + else + // Use CPU to figure out the exact features + ARMArchFeature = "+v8"; } else if (SubVer == '7') { if (Len >= Idx+2 && TT[Idx+1] == 'm') { isThumb = true; diff --git a/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll b/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll index 2a31703..3501fb7 100644 --- a/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll +++ b/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll @@ -5,10 +5,10 @@ ; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=V7 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8 ; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi | FileCheck %s --check-prefix=Vt8 -; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+fp-armv8 | FileCheck %s --check-prefix=V8-FPARMv8 -; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+neon | FileCheck %s --check-prefix=V8-NEON -; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+fp-armv8 -mattr=+neon | FileCheck %s --check-prefix=V8-FPARMv8-NEON -; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+fp-armv8,+neon,+crypto | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-neon,-crypto | FileCheck %s --check-prefix=V8-FPARMv8 +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-fp-armv8,-crypto | FileCheck %s --check-prefix=V8-NEON +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-crypto | FileCheck %s --check-prefix=V8-FPARMv8-NEON +; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 | FileCheck %s --check-prefix=CORTEX-A9 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CORTEX-M4 @@ -140,8 +140,12 @@ ; CORTEX-A53: .eabi_attribute 7, 65 ; CORTEX-A53: .eabi_attribute 8, 1 ; CORTEX-A53: .eabi_attribute 9, 2 +; CORTEX-A53: .fpu crypto-neon-fp-armv8 +; CORTEX-A53: .eabi_attribute 10, 7 +; CORTEX-A53: .eabi_attribute 12, 3 ; CORTEX-A53: .eabi_attribute 24, 1 ; CORTEX-A53: .eabi_attribute 25, 1 +; CORTEX-A53: .eabi_attribute 44, 2 define i32 @f(i64 %z) { ret i32 0 diff --git a/test/MC/ARM/invalid-fp-armv8.s b/test/MC/ARM/invalid-fp-armv8.s index d640dc1..21adb7e 100644 --- a/test/MC/ARM/invalid-fp-armv8.s +++ b/test/MC/ARM/invalid-fp-armv8.s @@ -1,4 +1,4 @@ -@ RUN: not llvm-mc -triple armv8 -show-encoding -mattr=+fp-armv8 < %s 2>&1 | FileCheck %s --check-prefix=V8 +@ RUN: not llvm-mc -triple armv8 -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=V8 @ VCVT{B,T} diff --git a/test/MC/ARM/invalid-neon-v8.s b/test/MC/ARM/invalid-neon-v8.s index 7aaf277..361946d 100644 --- a/test/MC/ARM/invalid-neon-v8.s +++ b/test/MC/ARM/invalid-neon-v8.s @@ -1,4 +1,4 @@ -@ RUN: not llvm-mc -triple armv8 -mattr=+neon,+crypto -show-encoding < %s 2>&1 | FileCheck %s +@ RUN: not llvm-mc -triple armv8 -mattr=-fp-armv8 -show-encoding < %s 2>&1 | FileCheck %s vmaxnm.f32 s4, d5, q1 @ CHECK: error: invalid operand for instruction |