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| author | Johnny Chen <johnny.chen@apple.com> | 2011-05-22 17:51:04 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-05-22 17:51:04 +0000 |
| commit | 75f4296c7c96499f4d8cdf90d5159f7965f94fd8 (patch) | |
| tree | e3c7e6bf86fc671ed5fd9178fb3a89f6b54c79a0 | |
| parent | 4f81b5419295cfc26a1349d6c23a55c6d2a683e1 (diff) | |
| download | external_llvm-75f4296c7c96499f4d8cdf90d5159f7965f94fd8.zip external_llvm-75f4296c7c96499f4d8cdf90d5159f7965f94fd8.tar.gz external_llvm-75f4296c7c96499f4d8cdf90d5159f7965f94fd8.tar.bz2 | |
Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx
Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and
modified ARMDisassemblerCore.cpp a little bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131859 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 9 | ||||
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 7 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/arm-tests.txt | 3 |
3 files changed, 16 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 59a9cd7..e9e11b0 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1313,6 +1313,15 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { let Inst{3-0} = dst; } + // For disassembly only. + def BX_pred : AXI<(outs), (ins GPR:$dst, pred:$p), BrMiscFrm, IIC_Br, + "bx$p\t$dst", [/* pattern left blank */]>, + Requires<[IsARM, HasV4T]> { + bits<4> dst; + let Inst{27-4} = 0b000100101111111111110001; + let Inst{3-0} = dst; + } + // ARMV4 only // FIXME: We would really like to define this as a vanilla ARMPat like: // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)> diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 642829c..271ca8c 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -895,8 +895,9 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn, } // Misc. Branch Instructions. -// BLX, BLXi, BX -// BX, BX_RET +// BX_RET, MOVPCLR +// BLX, BLX_pred, BX, BX_pred +// BLXi static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { @@ -913,7 +914,7 @@ static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, // BLX and BX take one GPR reg. if (Opcode == ARM::BLX || Opcode == ARM::BLX_pred || - Opcode == ARM::BX) { + Opcode == ARM::BX || Opcode == ARM::BX_pred) { assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID && "Reg operand expected"); MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index ade2952..ca072c7 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -164,6 +164,9 @@ # CHECK: bx r12 0x1c 0xff 0x2f 0xe1 +# CHECK: bxeq r5 +0x15 0xff 0x2f 0x01 + # CHECK: uqadd16mi r6, r11, r8 0x18 0x60 0x6b 0x46 |