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| author | Evan Cheng <evan.cheng@apple.com> | 2007-03-21 00:16:56 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-03-21 00:16:56 +0000 |
| commit | 768143547ba66c8cbeef09d4234ae908bbf5b9f8 (patch) | |
| tree | b8d4bbf5d89d0dc0f701f50d198717cc6a008dd9 | |
| parent | a125cbe839398f7df475e322bdaf150c62a1c8c3 (diff) | |
| download | external_llvm-768143547ba66c8cbeef09d4234ae908bbf5b9f8.zip external_llvm-768143547ba66c8cbeef09d4234ae908bbf5b9f8.tar.gz external_llvm-768143547ba66c8cbeef09d4234ae908bbf5b9f8.tar.bz2 | |
Mark re-materializable instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35230 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86InstrFPStack.td | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 2 |
3 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td index 48b216a..848d370 100644 --- a/lib/Target/X86/X86InstrFPStack.td +++ b/lib/Target/X86/X86InstrFPStack.td @@ -413,10 +413,12 @@ def FSTPrr : FPI<0xD8, AddRegFrm, (ops RST:$op), "fstp $op">, DD; def FXCH : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9; // Floating point constant loads. +let isReMaterializable = 1 in { def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP, [(set RFP:$dst, fp64imm0)]>; def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP, [(set RFP:$dst, fp64imm1)]>; +} def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9; def FLD1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9; diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 50bef56..fd08e47 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -601,6 +601,7 @@ def MOV16rr : I<0x89, MRMDestReg, (ops GR16:$dst, GR16:$src), "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; def MOV32rr : I<0x89, MRMDestReg, (ops GR32:$dst, GR32:$src), "mov{l} {$src, $dst|$dst, $src}", []>; +let isReMaterializable = 1 in { def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops GR8 :$dst, i8imm :$src), "mov{b} {$src, $dst|$dst, $src}", [(set GR8:$dst, imm:$src)]>; @@ -610,6 +611,7 @@ def MOV16ri : Ii16<0xB8, AddRegFrm, (ops GR16:$dst, i16imm:$src), def MOV32ri : Ii32<0xB8, AddRegFrm, (ops GR32:$dst, i32imm:$src), "mov{l} {$src, $dst|$dst, $src}", [(set GR32:$dst, imm:$src)]>; +} def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src), "mov{b} {$src, $dst|$dst, $src}", [(store (i8 imm:$src), addr:$dst)]>; diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index dff6416..82831f7 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -1666,6 +1666,7 @@ def MWAIT : I<0xC9, RawFrm, (ops), "mwait", // Alias instructions that map zero vector to pxor / xorp* for sse. // FIXME: remove when we can teach regalloc that xor reg, reg is ok. +let isReMaterializable = 1 in { def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst), "xorps $dst, $dst", [(set VR128:$dst, (v4f32 immAllZerosV))]>; @@ -1673,6 +1674,7 @@ def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst), def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst), "pcmpeqd $dst, $dst", [(set VR128:$dst, (v2f64 immAllOnesV))]>; +} // FR32 / FR64 to 128-bit vector conversion. def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src), |