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| author | Duncan Sands <baldrick@free.fr> | 2008-07-17 17:35:14 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2008-07-17 17:35:14 +0000 |
| commit | 79ada108dd0d85af15d301be5479992a2d54e5ba (patch) | |
| tree | a7990d3249d68a54e64e1125fa9bf9e2cb983c1c | |
| parent | 29681a53857b929fc8b4373884b8d958a144b9b7 (diff) | |
| download | external_llvm-79ada108dd0d85af15d301be5479992a2d54e5ba.zip external_llvm-79ada108dd0d85af15d301be5479992a2d54e5ba.tar.gz external_llvm-79ada108dd0d85af15d301be5479992a2d54e5ba.tar.bz2 | |
LegalizeTypes support for what seems to be the
only missing ppc long double operations: FNEG
and FP_EXTEND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53723 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp | 16 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeTypes.h | 2 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/2008-07-17-Fneg.ll | 18 |
3 files changed, 36 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index b1edae8..888cec0 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -531,6 +531,8 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) { case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break; case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break; case ISD::FMUL: ExpandFloatRes_FMUL(N, Lo, Hi); break; + case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break; + case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break; case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break; case ISD::LOAD: ExpandFloatRes_LOAD(N, Lo, Hi); break; case ISD::SINT_TO_FP: @@ -609,6 +611,20 @@ void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDOperand &Lo, Lo = Call.getOperand(0); Hi = Call.getOperand(1); } +void DAGTypeLegalizer::ExpandFloatRes_FNEG(SDNode *N, SDOperand &Lo, + SDOperand &Hi) { + GetExpandedFloat(N->getOperand(0), Lo, Hi); + Lo = DAG.getNode(ISD::FNEG, Lo.getValueType(), Lo); + Hi = DAG.getNode(ISD::FNEG, Hi.getValueType(), Hi); +} + +void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDOperand &Lo, + SDOperand &Hi) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + Hi = DAG.getNode(ISD::FP_EXTEND, NVT, N->getOperand(0)); + Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT); +} + void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDOperand &Lo, SDOperand &Hi) { SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h index 1959df5..f6a5c69 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -374,6 +374,8 @@ private: void ExpandFloatRes_FADD (SDNode *N, SDOperand &Lo, SDOperand &Hi); void ExpandFloatRes_FDIV (SDNode *N, SDOperand &Lo, SDOperand &Hi); void ExpandFloatRes_FMUL (SDNode *N, SDOperand &Lo, SDOperand &Hi); + void ExpandFloatRes_FNEG (SDNode *N, SDOperand &Lo, SDOperand &Hi); + void ExpandFloatRes_FP_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi); void ExpandFloatRes_FSUB (SDNode *N, SDOperand &Lo, SDOperand &Hi); void ExpandFloatRes_LOAD (SDNode *N, SDOperand &Lo, SDOperand &Hi); void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDOperand &Lo, SDOperand &Hi); diff --git a/test/CodeGen/PowerPC/2008-07-17-Fneg.ll b/test/CodeGen/PowerPC/2008-07-17-Fneg.ll new file mode 100644 index 0000000..54bb4b3 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-07-17-Fneg.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin9" + +define hidden i64 @__fixunstfdi(ppc_fp128 %a) nounwind { +entry: + br i1 false, label %bb3, label %bb4 + +bb3: ; preds = %entry + sub ppc_fp128 0xM80000000000000000000000000000000, 0xM00000000000000000000000000000000 ; <ppc_fp128>:0 [#uses=1] + fptoui ppc_fp128 %0 to i32 ; <i32>:1 [#uses=1] + zext i32 %1 to i64 ; <i64>:2 [#uses=1] + sub i64 0, %2 ; <i64>:3 [#uses=1] + ret i64 %3 + +bb4: ; preds = %entry + ret i64 0 +} |