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authorRafael Espindola <rafael.espindola@gmail.com>2006-08-09 16:41:12 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2006-08-09 16:41:12 +0000
commit7a53bd0890b0529c6dd95e97611dca7a8c4d6077 (patch)
tree9ae47671a85c7936993df7ddcf6706c907243d55
parent2c8cdc6c1ad78179fecfe67e7e0e250a4053c714 (diff)
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fix the spill code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29583 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMISelDAGToDAG.cpp6
-rw-r--r--lib/Target/ARM/ARMRegisterInfo.cpp16
-rw-r--r--test/CodeGen/ARM/vargs.ll5
3 files changed, 18 insertions, 9 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 1ef5bf4..8d2cbfd 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -148,6 +148,12 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
Ops.push_back(Chain);
Ops.push_back(Callee);
+ // Add argument registers to the end of the list so that they are known live
+ // into the call.
+ for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
+ Ops.push_back(DAG.getRegister(RegsToPass[i].first,
+ RegsToPass[i].second.getValueType()));
+
unsigned CallOpc = ARMISD::CALL;
if (InFlag.Val)
Ops.push_back(InFlag);
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 9c60769..ba0cd91 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -31,9 +31,8 @@ void ARMRegisterInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, int FI,
const TargetRegisterClass *RC) const {
- // On the order of operands here: think "[FI + 0] = SrcReg".
assert (RC == ARM::IntRegsRegisterClass);
- BuildMI(MBB, I, ARM::str, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
+ BuildMI(MBB, I, ARM::str, 3).addReg(SrcReg).addImm(0).addFrameIndex(FI);
}
void ARMRegisterInfo::
@@ -41,7 +40,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FI,
const TargetRegisterClass *RC) const {
assert (RC == ARM::IntRegsRegisterClass);
- BuildMI(MBB, I, ARM::ldr, 2, DestReg).addFrameIndex(FI).addImm(0);
+ BuildMI(MBB, I, ARM::ldr, 2, DestReg).addImm(0).addFrameIndex(FI);
}
void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
@@ -81,7 +80,8 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
- assert (MI.getOpcode() == ARM::ldr);
+ assert (MI.getOpcode() == ARM::ldr ||
+ MI.getOpcode() == ARM::str);
unsigned FrameIdx = 2;
unsigned OffIdx = 1;
@@ -93,6 +93,11 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
unsigned StackSize = MF.getFrameInfo()->getStackSize();
+ //<hack>
+ if (Offset < 0)
+ Offset -= 4;
+ //</hack>
+
Offset += StackSize;
assert (Offset >= 0);
@@ -121,9 +126,6 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
MachineFrameInfo *MFI = MF.getFrameInfo();
int NumBytes = (int) MFI->getStackSize();
- //hack
- assert(NumBytes == 0);
-
if (MFI->hasCalls()) {
// We reserve argument space for call sites in the function immediately on
// entry to the current function. This eliminates the need for add/sub
diff --git a/test/CodeGen/ARM/vargs.ll b/test/CodeGen/ARM/vargs.ll
index 858c463..f60c51a 100644
--- a/test/CodeGen/ARM/vargs.ll
+++ b/test/CodeGen/ARM/vargs.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=arm
+; RUN: llvm-as < %s | llc -march=arm
%str = internal constant [43 x sbyte] c"Hello World %d %d %d %d %d %d %d %d %d %d\0A\00" ; <[43 x sbyte]*> [#uses=1]
implementation ; Functions:
@@ -6,7 +6,8 @@ implementation ; Functions:
int %main() {
entry:
%tmp = call int (sbyte*, ...)* %printf( sbyte* getelementptr ([43 x sbyte]* %str, int 0, uint 0), int 1, int 2, int 3, int 4, int 5, int 6, int 7, int 8, int 9, int 10 ) ; <int> [#uses=0]
- ret int 0
+ %tmp2 = call int (sbyte*, ...)* %printf( sbyte* getelementptr ([43 x sbyte]* %str, int 0, uint 0), int 10, int 9, int 8, int 7, int 6, int 5, int 4, int 3, int 2, int 1 ) ; <int> [#uses=0]
+ ret int 11
}
declare int %printf(sbyte*, ...)