Switch name from tblgen -> llvm-tblgen for consistency with upstream LLVM.

Change-Id: I7735fd88104ff95001dd5f88a1c387df9af993ad

5 files changed, 29 insertions, 29 deletions

diff --git a/llvm-device-build.mk b/llvm-device-build.mk
index 107762a..82ef055 100644
--- a/llvm-device-build.mk
+++ b/llvm-device-build.mk
@@ -70,7 +70,7 @@ LOCAL_C_INCLUDES :=	\
 define transform-device-td-to-out
 @mkdir -p $(dir $@)
 @echo "Device TableGen (gen-$(1)): $(TBLGEN_LOCAL_MODULE) <= $<"
-$(hide) $(TBLGEN) \
+$(hide) $(LLVM_TBLGEN) \
 	-I $(dir $<)	\
 	-I $(LLVM_ROOT_PATH)/include	\
 	-I $(LLVM_ROOT_PATH)/device/include	\
diff --git a/llvm-gen-intrinsics.mk b/llvm-gen-intrinsics.mk
index 358027b..4fc7b76 100644
--- a/llvm-gen-intrinsics.mk
+++ b/llvm-gen-intrinsics.mk
@@ -11,7 +11,7 @@ endif
 GENFILE := $(addprefix $(call local-generated-sources-dir)/llvm/IR/,Intrinsics.gen)
 LOCAL_GENERATED_SOURCES += $(GENFILE)
 $(GENFILE): TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
-$(GENFILE): $(INTRINSICTD) $(INTRINSICTDS) | $(TBLGEN)
+$(GENFILE): $(INTRINSICTD) $(INTRINSICTDS) | $(LLVM_TBLGEN)
 ifeq ($(LOCAL_IS_HOST_MODULE),true)
 	$(call transform-host-td-to-out,intrinsic)
 else
diff --git a/llvm-host-build.mk b/llvm-host-build.mk
index c68d455..8c14f28 100644
--- a/llvm-host-build.mk
+++ b/llvm-host-build.mk
@@ -59,7 +59,7 @@ LOCAL_IS_HOST_MODULE := true
 define transform-host-td-to-out
 @mkdir -p $(dir $@)
 @echo "Host TableGen: $(TBLGEN_LOCAL_MODULE) (gen-$(1)) <= $<"
-$(hide) $(TBLGEN) \
+$(hide) $(LLVM_TBLGEN) \
 	-I $(dir $<)	\
 	-I $(LLVM_ROOT_PATH)/include	\
 	-I $(LLVM_ROOT_PATH)/host/include	\
diff --git a/llvm-tblgen-rules.mk b/llvm-tblgen-rules.mk
index 0746e8b..57be1a7 100644
--- a/llvm-tblgen-rules.mk
+++ b/llvm-tblgen-rules.mk
@@ -41,51 +41,51 @@ tblgen_td_deps := $(wildcard $(tblgen_td_deps))
 ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/ARM/MCTargetDesc)
 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
-                                       $(tblgen_td_deps) | $(TBLGEN)
+                                       $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out, register-info)
 
 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
-                                    $(tblgen_td_deps) | $(TBLGEN)
+                                    $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,instr-info)
 
 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
-                                        $(tblgen_td_deps) | $(TBLGEN)
+                                        $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,subtarget)
 endif
 
 ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/X86/MCTargetDesc)
 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
-                                       $(tblgen_td_deps) | $(TBLGEN)
+                                       $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out, register-info)
 
 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
-                                    $(tblgen_td_deps) | $(TBLGEN)
+                                    $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,instr-info)
 
 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
-                                        $(tblgen_td_deps) | $(TBLGEN)
+                                        $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,subtarget)
 endif
 
 ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/Mips/MCTargetDesc)
 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
-                                       $(tblgen_td_deps) | $(TBLGEN)
+                                       $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out, register-info)
 
 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
-                                    $(tblgen_td_deps) | $(TBLGEN)
+                                    $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,instr-info)
 
 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
-                                        $(tblgen_td_deps) | $(TBLGEN)
+                                        $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,subtarget)
 endif
 
@@ -93,112 +93,112 @@ endif
 ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td \
-                                       $(tblgen_td_deps) | $(TBLGEN)
+                                       $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,register-info)
 endif
 
 ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td \
-                                    $(tblgen_td_deps) | $(TBLGEN)
+                                    $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,instr-info)
 endif
 
 ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/%GenAsmWriter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td \
-                                    $(tblgen_td_deps) | $(TBLGEN)
+                                    $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,asm-writer)
 endif
 
 ifneq ($(filter %GenAsmWriter1.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/%GenAsmWriter1.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td \
-                                     $(tblgen_td_deps) | $(TBLGEN)
+                                     $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,asm-writer -asmwriternum=1)
 endif
 
 ifneq ($(filter %GenAsmMatcher.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/%GenAsmMatcher.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td \
-                                     $(tblgen_td_deps) | $(TBLGEN)
+                                     $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,asm-matcher)
 endif
 
 ifneq ($(filter %GenCodeEmitter.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/%GenCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td \
-                                      $(tblgen_td_deps) | $(TBLGEN)
+                                      $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,emitter)
 endif
 
 ifneq ($(filter %GenMCCodeEmitter.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/%GenMCCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td \
-                                        $(tblgen_td_deps) | $(TBLGEN)
+                                        $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,emitter -mc-emitter)
 endif
 
 ifneq ($(filter %GenMCPseudoLowering.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/%GenMCPseudoLowering.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td \
-                                           $(tblgen_td_deps) | $(TBLGEN)
+                                           $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,pseudo-lowering)
 endif
 
 ifneq ($(filter %GenDAGISel.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/%GenDAGISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td \
-                                  $(tblgen_td_deps) | $(TBLGEN)
+                                  $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,dag-isel)
 endif
 
 ifneq ($(filter %GenDisassemblerTables.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/%GenDisassemblerTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td \
-                                             $(tblgen_td_deps) | $(TBLGEN)
+                                             $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,disassembler)
 endif
 
 ifneq ($(filter %GenEDInfo.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/%GenEDInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td \
-                                 $(tblgen_td_deps) | $(TBLGEN)
+                                 $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,enhanced-disassembly-info)
 endif
 
 ifneq ($(filter %GenFastISel.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/%GenFastISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenFastISel.inc: $(tblgen_source_dir)/%.td \
-                                   $(tblgen_td_deps) | $(TBLGEN)
+                                   $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,fast-isel)
 endif
 
 ifneq ($(filter %GenSubtargetInfo.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td \
-                                        $(tblgen_td_deps) | $(TBLGEN)
+                                        $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,subtarget)
 endif
 
 ifneq ($(filter %GenCallingConv.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/%GenCallingConv.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td \
-                                      $(tblgen_td_deps) | $(TBLGEN)
+                                      $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,callingconv)
 endif
 
 ifneq ($(filter %GenIntrinsics.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/%GenIntrinsics.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td \
-                                     $(tblgen_td_deps) | $(TBLGEN)
+                                     $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,tgt_intrinsics)
 endif
 
 ifneq ($(findstring ARMGenDecoderTables.inc,$(tblgen_gen_tables)),)
 $(generated_sources)/ARMGenDecoderTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 $(generated_sources)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td \
-                                          $(tblgen_td_deps) | $(TBLGEN)
+                                          $(tblgen_td_deps) | $(LLVM_TBLGEN)
 	$(call transform-td-to-out,arm-decoder)
 endif
 
diff --git a/utils/TableGen/Android.mk b/utils/TableGen/Android.mk
index 8117672..c982168 100644
--- a/utils/TableGen/Android.mk
+++ b/utils/TableGen/Android.mk
@@ -36,7 +36,7 @@ tablegen_SRC_FILES := \
 
 include $(CLEAR_VARS)
 
-LOCAL_MODULE := tblgen
+LOCAL_MODULE := llvm-tblgen
 LOCAL_MODULE_TAGS := optional
 LOCAL_SRC_FILES := $(tablegen_SRC_FILES)