- Remove dead patterns.

- Add encodings to the *LDMIA_RET instrs. Probably not needed...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119323 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 19 insertions, 43 deletions

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 39ae973..4abb567 100644
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -834,38 +834,6 @@ class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
   let Inst{19-16} = Rn;
   let Inst{15-0}  = regs;
 }
-class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
-             string asm, string cstr, list<dag> pattern>
-  : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
-       asm, cstr, pattern> {
-  bits<4> p;
-  bits<16> dsts;
-  bits<4> Rn;
-  bits<2> amode;
-  let Inst{31-28} = p;
-  let Inst{27-25} = 0b100;
-  let Inst{24-23} = amode;
-  let Inst{22}    = 0; // S bit
-  let Inst{20}    = 1; // L bit
-  let Inst{19-16} = Rn;
-  let Inst{15-0}  = dsts;
-}
-class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
-             string asm, string cstr, list<dag> pattern>
-  : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
-       asm, cstr, pattern> {
-  bits<4> p;
-  bits<16> srcs;
-  bits<4> Rn;
-  bits<2> amode;
-  let Inst{31-28} = p;
-  let Inst{27-25} = 0b100;
-  let Inst{24-23} = amode;
-  let Inst{22}    = 0; // S bit
-  let Inst{20}    = 0; // L bit
-  let Inst{19-16} = Rn;
-  let Inst{15-0}  = srcs;
-}
 
 // Unsigned multiply, multiply-accumulate instructions.
 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 0c7c0b8..5495551 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1869,16 +1869,16 @@ def : MnemonicAlias<"stm", "stmia">;
 // FIXME: Should pc be an implicit operand like PICADD, etc?
 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
     hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
-def LDMIA_RET : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
-                                        reglist:$dsts, variable_ops),
-                       IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
-                       "ldmia${p}\t$Rn!, $dsts",
-                       "$Rn = $wb", []> {
-  let Inst{24-23} = 0b01;     // Increment After
-  let Inst{21}    = 1;        // Writeback
+def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
+                                      reglist:$dsts, variable_ops),
+                     IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
+                     "ldmia${p}\t$Rn!, $dsts",
+                     "$Rn = $wb", []> {
+  let Inst{24-23} = 0b01;       // Increment After
+  let Inst{21}    = 1;          // Writeback
+  let Inst{20}    = 1;          // Load
 }
 
-
 //===----------------------------------------------------------------------===//
 //  Move Instructions.
 //
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index e9d5212..5e3a598 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -2764,9 +2764,17 @@ def t2LDMIA_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
                         IIC_iLoad_mBr,
                         "ldmia${p}.w\t$Rn!, $dsts",
                         "$Rn = $wb", []> {
-  let Inst{24-23} = 0b01; // IA: '01', DB: '10'
-  let Inst{21}    = 1; // The W bit.
-  let Inst{20}    = 1; // Load
+  bits<4>  Rn;
+  bits<16> regs;
+ 
+  let Inst{31-27} = 0b11101;
+  let Inst{26-25} = 0b00;
+  let Inst{24-23} = 0b01;     // Increment After
+  let Inst{22}    = 0;
+  let Inst{21}    = 1;        // Writeback
+  let Inst{20}    = L_bit;
+  let Inst{19-16} = Rn;
+  let Inst{15-0}  = regs;
 }
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {