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| author | Evan Cheng <evan.cheng@apple.com> | 2006-11-28 01:28:00 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-11-28 01:28:00 +0000 |
| commit | 7bb64e8369318c962232e051c0b0b2f434fcecdf (patch) | |
| tree | 74344361574192ecf32d58a621bc98343519b246 | |
| parent | 7b0948731aaeca1df43f45ee24fb26050551f196 (diff) | |
| download | external_llvm-7bb64e8369318c962232e051c0b0b2f434fcecdf.zip external_llvm-7bb64e8369318c962232e051c0b0b2f434fcecdf.tar.gz external_llvm-7bb64e8369318c962232e051c0b0b2f434fcecdf.tar.bz2 | |
Fix JIT encoding bugs for shift / rotate by one ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31952 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86InstrX86-64.td | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/X86/X86InstrX86-64.td b/lib/Target/X86/X86InstrX86-64.td index 3042802..0e024d1 100644 --- a/lib/Target/X86/X86InstrX86-64.td +++ b/lib/Target/X86/X86InstrX86-64.td @@ -466,7 +466,7 @@ def SHL64mCL : RI<0xD3, MRM4m, (ops i64mem:$dst), def SHL64mi : RIi8<0xC1, MRM4m, (ops i64mem:$dst, i8imm:$src), "shl{q} {$src, $dst|$dst, $src}", [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; -def SHL64m1 : RI<0xC1, MRM4m, (ops i64mem:$dst), +def SHL64m1 : RI<0xD1, MRM4m, (ops i64mem:$dst), "shl{q} $dst", [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; @@ -490,7 +490,7 @@ def SHR64mCL : RI<0xD3, MRM5m, (ops i64mem:$dst), def SHR64mi : RIi8<0xC1, MRM5m, (ops i64mem:$dst, i8imm:$src), "shr{q} {$src, $dst|$dst, $src}", [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; -def SHR64m1 : RI<0xC1, MRM5m, (ops i64mem:$dst), +def SHR64m1 : RI<0xD1, MRM5m, (ops i64mem:$dst), "shr{q} $dst", [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; @@ -513,7 +513,7 @@ def SAR64mCL : RI<0xD3, MRM7m, (ops i64mem:$dst), def SAR64mi : RIi8<0xC1, MRM7m, (ops i64mem:$dst, i8imm:$src), "sar{q} {$src, $dst|$dst, $src}", [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; -def SAR64m1 : RI<0xC1, MRM7m, (ops i64mem:$dst), +def SAR64m1 : RI<0xD1, MRM7m, (ops i64mem:$dst), "sar{q} $dst", [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; @@ -525,7 +525,7 @@ def ROL64rCL : RI<0xD3, MRM0r, (ops GR64:$dst, GR64:$src), def ROL64ri : RIi8<0xC1, MRM0r, (ops GR64:$dst, GR64:$src1, i8imm:$src2), "rol{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>; -def ROL64r1 : RI<0xC1, MRM0r, (ops GR64:$dst, GR64:$src1), +def ROL64r1 : RI<0xD1, MRM0r, (ops GR64:$dst, GR64:$src1), "rol{q} $dst", [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>; } // isTwoAddress @@ -548,7 +548,7 @@ def ROR64rCL : RI<0xD3, MRM1r, (ops GR64:$dst, GR64:$src), def ROR64ri : RIi8<0xC1, MRM1r, (ops GR64:$dst, GR64:$src1, i8imm:$src2), "ror{q} {$src2, $dst|$dst, $src2}", [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>; -def ROR64r1 : RI<0xC1, MRM1r, (ops GR64:$dst, GR64:$src1), +def ROR64r1 : RI<0xD1, MRM1r, (ops GR64:$dst, GR64:$src1), "ror{q} $dst", [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>; } // isTwoAddress |