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| author | Nowar Gu <nowar100@gmail.com> | 2011-07-02 11:57:29 +0800 |
|---|---|---|
| committer | Nowar Gu <nowar100@gmail.com> | 2011-07-02 11:57:29 +0800 |
| commit | 7c328f3347b42249c4178432bc29ca66271617a9 (patch) | |
| tree | 84bef9d6d106ca3c9b54f468865bff3cb9baebfe | |
| parent | 1ffcf07d9fb7a7db5737ca7307ae8e0aa713f278 (diff) | |
| download | external_llvm-7c328f3347b42249c4178432bc29ca66271617a9.zip external_llvm-7c328f3347b42249c4178432bc29ca66271617a9.tar.gz external_llvm-7c328f3347b42249c4178432bc29ca66271617a9.tar.bz2 | |
Fix Android.mk.
| -rw-r--r-- | lib/MC/Android.mk | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/Android.mk | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/AsmParser/Android.mk | 3 | ||||
| -rw-r--r-- | lib/Target/Android.mk | 2 | ||||
| -rw-r--r-- | lib/Target/X86/Android.mk | 2 | ||||
| -rw-r--r-- | lib/Target/X86/AsmParser/Android.mk | 3 | ||||
| -rw-r--r-- | lib/Target/X86/InstPrinter/Android.mk | 3 | ||||
| -rw-r--r-- | llvm-tblgen-rules.mk | 4 |
8 files changed, 12 insertions, 8 deletions
diff --git a/lib/MC/Android.mk b/lib/MC/Android.mk index 43062da..e46b9bf 100644 --- a/lib/MC/Android.mk +++ b/lib/MC/Android.mk @@ -30,6 +30,7 @@ mc_SRC_FILES := \ MCSectionELF.cpp \ MCSectionMachO.cpp \ MCStreamer.cpp \ + MCSubtargetInfo.cpp \ MCSymbol.cpp \ MCValue.cpp \ MCWin64EH.cpp \ diff --git a/lib/Target/ARM/Android.mk b/lib/Target/ARM/Android.mk index 91d84cc..5dbbc17 100644 --- a/lib/Target/ARM/Android.mk +++ b/lib/Target/ARM/Android.mk @@ -7,7 +7,7 @@ arm_codegen_TBLGEN_TABLES := \ ARMGenInstrInfo.inc \ ARMGenDAGISel.inc \ ARMGenFastISel.inc \ - ARMGenSubtarget.inc \ + ARMGenSubtargetInfo.inc \ ARMGenCodeEmitter.inc \ ARMGenCallingConv.inc diff --git a/lib/Target/ARM/AsmParser/Android.mk b/lib/Target/ARM/AsmParser/Android.mk index 664de6c..57678e0 100644 --- a/lib/Target/ARM/AsmParser/Android.mk +++ b/lib/Target/ARM/AsmParser/Android.mk @@ -8,7 +8,8 @@ include $(CLEAR_TBLGEN_VARS) TBLGEN_TABLES := \ ARMGenInstrInfo.inc \ ARMGenRegisterInfo.inc \ - ARMGenAsmMatcher.inc + ARMGenAsmMatcher.inc \ + ARMGenSubtargetInfo.inc TBLGEN_TD_DIR := $(LOCAL_PATH)/.. diff --git a/lib/Target/Android.mk b/lib/Target/Android.mk index 1c668d8..ddbe63a 100644 --- a/lib/Target/Android.mk +++ b/lib/Target/Android.mk @@ -14,7 +14,7 @@ target_SRC_FILES := \ TargetLibraryInfo.cpp \ TargetMachine.cpp \ TargetRegisterInfo.cpp \ - TargetSubtarget.cpp + TargetSubtargetInfo.cpp # For the host # ===================================================== diff --git a/lib/Target/X86/Android.mk b/lib/Target/X86/Android.mk index 3e95a31..537e462 100644 --- a/lib/Target/X86/Android.mk +++ b/lib/Target/X86/Android.mk @@ -7,7 +7,7 @@ x86_codegen_TBLGEN_TABLES := \ X86GenInstrInfo.inc \ X86GenDAGISel.inc \ X86GenFastISel.inc \ - X86GenSubtarget.inc \ + X86GenSubtargetInfo.inc \ X86GenCallingConv.inc x86_codegen_SRC_FILES := \ diff --git a/lib/Target/X86/AsmParser/Android.mk b/lib/Target/X86/AsmParser/Android.mk index faeaae6..fc501ec 100644 --- a/lib/Target/X86/AsmParser/Android.mk +++ b/lib/Target/X86/AsmParser/Android.mk @@ -8,7 +8,8 @@ include $(CLEAR_TBLGEN_VARS) TBLGEN_TABLES := \ X86GenAsmMatcher.inc \ X86GenInstrInfo.inc \ - X86GenRegisterInfo.inc + X86GenRegisterInfo.inc \ + X86GenSubtargetInfo.inc TBLGEN_TD_DIR := $(LOCAL_PATH)/.. diff --git a/lib/Target/X86/InstPrinter/Android.mk b/lib/Target/X86/InstPrinter/Android.mk index 11c9244..0fd7058 100644 --- a/lib/Target/X86/InstPrinter/Android.mk +++ b/lib/Target/X86/InstPrinter/Android.mk @@ -4,7 +4,8 @@ x86_instprinter_TBLGEN_TABLES := \ X86GenAsmWriter.inc \ X86GenAsmWriter1.inc \ X86GenInstrInfo.inc \ - X86GenRegisterInfo.inc + X86GenRegisterInfo.inc \ + X86GenSubtargetInfo.inc x86_instprinter_SRC_FILES := \ X86ATTInstPrinter.cpp \ diff --git a/llvm-tblgen-rules.mk b/llvm-tblgen-rules.mk index 3da6950..eb14b04 100644 --- a/llvm-tblgen-rules.mk +++ b/llvm-tblgen-rules.mk @@ -83,8 +83,8 @@ $(intermediates)/%GenFastISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,fast-isel) endif -ifneq ($(filter %GenSubtarget.inc,$(tblgen_gen_tables)),) -$(intermediates)/%GenSubtarget.inc: $(tblgen_source_dir)/%.td $(TBLGEN) +ifneq ($(filter %GenSubtargetInfo.inc,$(tblgen_gen_tables)),) +$(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN) $(call transform-td-to-out,subtarget) endif |