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author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2011-03-04 12:00:11 +0000 |
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committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2011-03-04 12:00:11 +0000 |
commit | 7f5de8b4c64280587c2c9a9a0ba4e1ada7e050e5 (patch) | |
tree | 41940f56bf039958143853931d82bb79f18bb353 | |
parent | 786792784e898f29febb3e7270d54b0e21e3c904 (diff) | |
download | external_llvm-7f5de8b4c64280587c2c9a9a0ba4e1ada7e050e5.zip external_llvm-7f5de8b4c64280587c2c9a9a0ba4e1ada7e050e5.tar.gz external_llvm-7f5de8b4c64280587c2c9a9a0ba4e1ada7e050e5.tar.bz2 |
Allow load from constant on SPU.
A 'load <4 x i32>* null' crashes llc before this fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126995 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/CellSPU/SPUISelDAGToDAG.cpp | 7 | ||||
-rw-r--r-- | test/CodeGen/CellSPU/loads.ll | 7 | ||||
-rw-r--r-- | test/CodeGen/CellSPU/stores.ll | 8 |
3 files changed, 21 insertions, 1 deletions
diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index d226156..9351ffd 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -321,12 +321,17 @@ SPUDAGToDAGISel::SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base, // These match the addr256k operand type: EVT OffsVT = MVT::i16; SDValue Zero = CurDAG->getTargetConstant(0, OffsVT); + int64_t val; switch (N.getOpcode()) { case ISD::Constant: + val = dyn_cast<ConstantSDNode>(N.getNode())->getSExtValue(); + Base = CurDAG->getTargetConstant( val , MVT::i32); + Index = Zero; + return true; break; case ISD::ConstantPool: case ISD::GlobalAddress: - report_fatal_error("SPU SelectAFormAddr: Constant/Pool/Global not lowered."); + report_fatal_error("SPU SelectAFormAddr: Pool/Global not lowered."); /*NOTREACHED*/ case ISD::TargetConstant: diff --git a/test/CodeGen/CellSPU/loads.ll b/test/CodeGen/CellSPU/loads.ll index 03d7ad1..4771752 100644 --- a/test/CodeGen/CellSPU/loads.ll +++ b/test/CodeGen/CellSPU/loads.ll @@ -50,3 +50,10 @@ define i32 @load_misaligned( i32* %ptr ){ %rv = load i32* %ptr, align 2 ret i32 %rv } + +define <4 x i32> @load_null_vec( ) { +;CHECK: lqa +;CHECK: bi $lr + %rv = load <4 x i32>* null + ret <4 x i32> %rv +} diff --git a/test/CodeGen/CellSPU/stores.ll b/test/CodeGen/CellSPU/stores.ll index 7e0bf06..6ca5b08 100644 --- a/test/CodeGen/CellSPU/stores.ll +++ b/test/CodeGen/CellSPU/stores.ll @@ -171,3 +171,11 @@ define void @store_v8( <8 x float> %val, <8 x float>* %ptr ) store <8 x float> %val, <8 x float>* %ptr ret void } + +define void @store_null_vec( <4 x i32> %val ) { +; FIXME - this is for some reason compiled into a il+stqd, not a sta. +;CHECK: stqd +;CHECK: bi $lr + store <4 x i32> %val, <4 x i32>* null + ret void +} |