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author | Aaron Ballman <aaron@aaronballman.com> | 2013-07-17 19:43:13 +0000 |
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committer | Aaron Ballman <aaron@aaronballman.com> | 2013-07-17 19:43:13 +0000 |
commit | 7f6d84230c0e21b4f841a0b28a1e494fe327d2b7 (patch) | |
tree | 88ff906268967c591292f4530d0beb9c0ca45a71 | |
parent | 27d0c68617dee9c60efbc179c31b4a1bd28daa34 (diff) | |
download | external_llvm-7f6d84230c0e21b4f841a0b28a1e494fe327d2b7.zip external_llvm-7f6d84230c0e21b4f841a0b28a1e494fe327d2b7.tar.gz external_llvm-7f6d84230c0e21b4f841a0b28a1e494fe327d2b7.tar.bz2 |
Silencing an MSVC warning about signed vs unsigned comparison mismatches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186529 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index f5d5e5a..bf341b3 100644 --- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -781,7 +781,7 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) { // all cases and are sometimes shorter. Prefer to use RISBG for ANDs though, // since it is effectively a three-operand instruction in this case, // and since it can handle some masks that AND IMMEDIATE can't. - if (Count < (N->getOpcode() == ISD::AND ? 1 : 2)) + if (Count < (N->getOpcode() == ISD::AND ? 1U : 2U)) return 0; // Prefer register extensions like LLC over RISBG. |