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authorEric Christopher <echristo@apple.com>2012-07-02 23:22:25 +0000
committerEric Christopher <echristo@apple.com>2012-07-02 23:22:25 +0000
commit80c1b38eff2fb3200cdddb1ef6641d64de8496a8 (patch)
tree79f69381ac25c007a8f1c1fe997edfb55a50a2b2
parentc723eb1aef817d47feec620933ee1ec6005cdd14 (diff)
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Revert " mips32 long long register inline asm constraint support." as
it appears to be breaking the bots. This reverts commit 1b055ce320fa13f6f1ac81670d11b45e01f79876. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159619 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/Mips/MipsISelLowering.cpp2
-rw-r--r--test/CodeGen/Mips/inlineasm-operand-code.ll6
2 files changed, 0 insertions, 8 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index a7e2aa3..abf22bd 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -3355,8 +3355,6 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
case 'r':
if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
return std::make_pair(0U, &Mips::CPURegsRegClass);
- if (VT == MVT::i64 && !HasMips64)
- return std::make_pair(0U, &Mips::CPURegsRegClass);
if (VT == MVT::i64 && HasMips64)
return std::make_pair(0U, &Mips::CPU64RegsRegClass);
// This will generate an error message
diff --git a/test/CodeGen/Mips/inlineasm-operand-code.ll b/test/CodeGen/Mips/inlineasm-operand-code.ll
index d75f7f2..ca4f3e4 100644
--- a/test/CodeGen/Mips/inlineasm-operand-code.ll
+++ b/test/CodeGen/Mips/inlineasm-operand-code.ll
@@ -41,11 +41,5 @@ entry:
;CHECK: #NO_APP
tail call i32 asm sideeffect "addi $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
-; a long long in 32 bit mode (use to assert)
-;CHECK: #APP
-;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3
-;CHECK: #NO_APP
- tail call i64 asm sideeffect "addi $0,$1,$2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind
-
ret i32 0
}