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| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-09 19:13:29 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-09 19:13:29 +0000 |
| commit | 812402019264506bea49749b23d0ead1be9fde7c (patch) | |
| tree | b8fd3828ab61493f50afdd2e52fb5ae014cf27a2 | |
| parent | d7a5b2826cbef9d980893a41f39bab6948e9c852 (diff) | |
| download | external_llvm-812402019264506bea49749b23d0ead1be9fde7c.zip external_llvm-812402019264506bea49749b23d0ead1be9fde7c.tar.gz external_llvm-812402019264506bea49749b23d0ead1be9fde7c.tar.bz2 | |
Remove ClassPrefix variable as it's no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15586 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 1 | ||||
| -rw-r--r-- | lib/Target/Sparc/SparcInstrInfo.td | 1 | ||||
| -rw-r--r-- | lib/Target/SparcV8/SparcV8InstrInfo.td | 1 | ||||
| -rw-r--r-- | lib/Target/SparcV9/SparcV9.td | 1 | ||||
| -rw-r--r-- | lib/Target/Target.td | 1 |
5 files changed, 0 insertions, 5 deletions
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index bec1c5d..7e54786 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -56,7 +56,6 @@ class PPC32I<string name, bits<6> opcode, bit ppc64, bit vmx> : Instruction { let Name = name; let Namespace = "PPC32"; - let ClassPrefix = "PowerPC"; let Inst{0-5} = opcode; } diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 5e61d51..07491eb 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -19,7 +19,6 @@ class InstV8 : Instruction { // SparcV8 instruction baseline field bits<32> Inst; let Namespace = "V8"; - let ClassPrefix = "SparcV8"; bits<2> op; let Inst{31-30} = op; // Top two bits are the 'op' field diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td index 5e61d51..07491eb 100644 --- a/lib/Target/SparcV8/SparcV8InstrInfo.td +++ b/lib/Target/SparcV8/SparcV8InstrInfo.td @@ -19,7 +19,6 @@ class InstV8 : Instruction { // SparcV8 instruction baseline field bits<32> Inst; let Namespace = "V8"; - let ClassPrefix = "SparcV8"; bits<2> op; let Inst{31-30} = op; // Top two bits are the 'op' field diff --git a/lib/Target/SparcV9/SparcV9.td b/lib/Target/SparcV9/SparcV9.td index 2adc500..f78317d 100644 --- a/lib/Target/SparcV9/SparcV9.td +++ b/lib/Target/SparcV9/SparcV9.td @@ -24,7 +24,6 @@ class InstV9 : Instruction { // SparcV9 instruction baseline field bits<32> Inst; let Namespace = "V9"; - let ClassPrefix = "SparcV9"; bits<2> op; let Inst{31-30} = op; // Top two bits are the 'op' field diff --git a/lib/Target/Target.td b/lib/Target/Target.td index 6fada34..e111f85 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -108,7 +108,6 @@ class RegisterClass<ValueType regType, int alignment, list<Register> regList> { class Instruction { string Name = ""; // The opcode string for this instruction string Namespace = ""; - string ClassPrefix = ""; dag OperandList; // An dag containing the MI operand list. string AsmString = ""; // The .s format to print the instruction with. |