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authorEli Friedman <eli.friedman@gmail.com>2011-07-27 19:43:50 +0000
committerEli Friedman <eli.friedman@gmail.com>2011-07-27 19:43:50 +0000
commit84e7f7e26738077eca4ff5465088fac37194a937 (patch)
treedb798b87f2809c3edcad870cb2c28d8a6bf27d6e
parentabcd715fdfd786e59f68579f7a68007d46d5218b (diff)
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X86ISD::MEMBARRIER does not require SSE2; it doesn't actually generate any code, and all x86 processors will honor the required semantics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136249 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86InstrCompiler.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td
index adcc747..17464f3 100644
--- a/lib/Target/X86/X86InstrCompiler.td
+++ b/lib/Target/X86/X86InstrCompiler.td
@@ -532,7 +532,7 @@ def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
let hasSideEffects = 1 in
def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
"#MEMBARRIER",
- [(X86MemBarrier)]>, Requires<[HasSSE2]>;
+ [(X86MemBarrier)]>;
// TODO: Get this to fold the constant into the instruction.
let hasSideEffects = 1, Defs = [ESP], isCodeGenOnly = 1 in