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| author | Kevin Enderby <enderby@apple.com> | 2012-03-12 21:32:09 +0000 |
|---|---|---|
| committer | Kevin Enderby <enderby@apple.com> | 2012-03-12 21:32:09 +0000 |
| commit | 84faf659125cb354794e457fa5a8a8daad84760d (patch) | |
| tree | 7a6839491302358b23187a26eec79fc674c1b787 | |
| parent | a185362095c0a6138216e61d4a767b930bcc7826 (diff) | |
| download | external_llvm-84faf659125cb354794e457fa5a8a8daad84760d.zip external_llvm-84faf659125cb354794e457fa5a8a8daad84760d.tar.gz external_llvm-84faf659125cb354794e457fa5a8a8daad84760d.tar.bz2 | |
Added a missing error check for X86 assembly with mismatched base and index
registers not both being 64-bit or both being 32-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152580 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/AsmParser/X86AsmParser.cpp | 19 | ||||
| -rw-r--r-- | test/MC/X86/x86_errors.s | 4 |
2 files changed, 23 insertions, 0 deletions
diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index e05b50c..ce32c77 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -838,6 +838,7 @@ X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) { // If we reached here, then we just ate the ( of the memory operand. Process // the rest of the memory operand. unsigned BaseReg = 0, IndexReg = 0, Scale = 1; + SMLoc IndexLoc; if (getLexer().is(AsmToken::Percent)) { SMLoc StartLoc, EndLoc; @@ -851,6 +852,7 @@ X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) { if (getLexer().is(AsmToken::Comma)) { Parser.Lex(); // Eat the comma. + IndexLoc = Parser.getTok().getLoc(); // Following the comma we should have either an index register, or a scale // value. We don't support the later form, but we want to parse it @@ -912,6 +914,23 @@ X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) { SMLoc MemEnd = Parser.getTok().getLoc(); Parser.Lex(); // Eat the ')'. + // If we have both a base register and an index register make sure they are + // both 64-bit or 32-bit registers. + if (BaseReg != 0 && IndexReg != 0) { + if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) && + !X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) && + IndexReg != X86::RIZ) { + Error(IndexLoc, "index register is 32-bit, but base register is 64-bit"); + return 0; + } + if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) && + !X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) && + IndexReg != X86::EIZ){ + Error(IndexLoc, "index register is 64-bit, but base register is 32-bit"); + return 0; + } + } + return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, MemStart, MemEnd); } diff --git a/test/MC/X86/x86_errors.s b/test/MC/X86/x86_errors.s index 8f2e1af..f161e06 100644 --- a/test/MC/X86/x86_errors.s +++ b/test/MC/X86/x86_errors.s @@ -24,3 +24,7 @@ sysexitq // rdar://10710167 // 64: error: expected scale expression lea (%rsp, %rbp, $4), %rax + +// rdar://10423777 +// 64: error: index register is 32-bit, but base register is 64-bit +movq (%rsi,%ecx),%xmm0 |