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| author | Richard Osborne <richard@xmos.com> | 2010-03-10 18:12:27 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2010-03-10 18:12:27 +0000 |
| commit | 850f1cd3c0c6feefd64f389ecb0e078d0b2bd9db (patch) | |
| tree | 0868723515ac4101d0872fbada972a9418ce606f | |
| parent | 0965200ac21fb481557f256c86d057df13bbb55e (diff) | |
| download | external_llvm-850f1cd3c0c6feefd64f389ecb0e078d0b2bd9db.zip external_llvm-850f1cd3c0c6feefd64f389ecb0e078d0b2bd9db.tar.gz external_llvm-850f1cd3c0c6feefd64f389ecb0e078d0b2bd9db.tar.bz2 | |
Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit
expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all
operands are zero extended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98168 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/XCore/XCoreISelLowering.cpp | 31 | ||||
| -rw-r--r-- | test/CodeGen/XCore/addsub64.ll | 15 |
2 files changed, 44 insertions, 2 deletions
diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index 8249219..3b3bb6d 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -1342,11 +1342,13 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, } break; case ISD::ADD: { - // Fold expressions such as add(add(mul(x,y),a),b) -> lmul(x, y, a, b). + // Fold 32 bit expressions such as add(add(mul(x,y),a),b) -> + // lmul(x, y, a, b). The high result of lmul will be ignored. // This is only profitable if the intermediate results are unused // elsewhere. SDValue Mul0, Mul1, Addend0, Addend1; - if (isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) { + if (N->getValueType(0) == MVT::i32 && + isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) { SDValue Zero = DAG.getConstant(0, MVT::i32); SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(MVT::i32, MVT::i32), Mul0, @@ -1354,6 +1356,31 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, SDValue Result(Ignored.getNode(), 1); return Result; } + APInt HighMask = APInt::getHighBitsSet(64, 32); + // Fold 64 bit expression such as add(add(mul(x,y),a),b) -> + // lmul(x, y, a, b) if all operands are zero-extended. We do this + // before type legalization as it is messy to match the operands after + // that. + if (N->getValueType(0) == MVT::i64 && + isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) && + DAG.MaskedValueIsZero(Mul0, HighMask) && + DAG.MaskedValueIsZero(Mul1, HighMask) && + DAG.MaskedValueIsZero(Addend0, HighMask) && + DAG.MaskedValueIsZero(Addend1, HighMask)) { + SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + Mul0, DAG.getConstant(0, MVT::i32)); + SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + Mul1, DAG.getConstant(0, MVT::i32)); + SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + Addend0, DAG.getConstant(0, MVT::i32)); + SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + Addend1, DAG.getConstant(0, MVT::i32)); + SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, + DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L, + Addend0L, Addend1L); + SDValue Lo(Hi.getNode(), 1); + return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); + } } break; case ISD::STORE: { diff --git a/test/CodeGen/XCore/addsub64.ll b/test/CodeGen/XCore/addsub64.ll index 0432e5e..d062480 100644 --- a/test/CodeGen/XCore/addsub64.ll +++ b/test/CodeGen/XCore/addsub64.ll @@ -42,3 +42,18 @@ entry: ; CHECK: maccs: ; CHECK: maccs r1, r0, r3, r2 ; CHECK-NEXT: retsp 0 + +define i64 @lmul(i32 %a, i32 %b, i32 %c, i32 %d) { +entry: + %0 = zext i32 %a to i64 + %1 = zext i32 %b to i64 + %2 = zext i32 %c to i64 + %3 = zext i32 %d to i64 + %4 = mul i64 %1, %0 + %5 = add i64 %4, %2 + %6 = add i64 %5, %3 + ret i64 %6 +} +; CHECK: lmul: +; CHECK: lmul r1, r0, r1, r0, r2, r3 +; CHECK-NEXT: retsp 0 |