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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:22:03 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:22:03 +0000 |
| commit | 88797e58d2e6b68cb92ae5d21f2f4966642bbeab (patch) | |
| tree | f5d21cf58bb6e968da7e5fb67cb83b3fbb041b47 | |
| parent | dd21ccf7216e65b46274cdc857d12310846c05c6 (diff) | |
| download | external_llvm-88797e58d2e6b68cb92ae5d21f2f4966642bbeab.zip external_llvm-88797e58d2e6b68cb92ae5d21f2f4966642bbeab.tar.gz external_llvm-88797e58d2e6b68cb92ae5d21f2f4966642bbeab.tar.bz2 | |
Add some crude itin approximation for VFP load / stores on A9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100671 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMScheduleV7.td | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMScheduleV7.td b/lib/Target/ARM/ARMScheduleV7.td index f413aaf..2dc6217 100644 --- a/lib/Target/ARM/ARMScheduleV7.td +++ b/lib/Target/ARM/ARMScheduleV7.td @@ -804,6 +804,60 @@ def CortexA9Itineraries : ProcessorItineraries<[ InstrStage<2, [FU_DRegsN], 0, Reserved>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_NPipe]>], [1, 1, 1]>, + // + // Single-precision FP Load + // use FU_Issue to enforce the 1 load/store per cycle limit + InstrItinData<IIC_fpLoad32, [InstrStage<1, [FU_DRegsVFP], 0, Required>, + InstrStage<2, [FU_DRegsN], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>]>, + // + // Double-precision FP Load + // use FU_Issue to enforce the 1 load/store per cycle limit + InstrItinData<IIC_fpLoad64, [InstrStage<1, [FU_DRegsVFP], 0, Required>, + InstrStage<2, [FU_DRegsN], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>]>, + // + // FP Load Multiple + // use FU_Issue to enforce the 1 load/store per cycle limit + InstrItinData<IIC_fpLoadm, [InstrStage<1, [FU_DRegsVFP], 0, Required>, + InstrStage<2, [FU_DRegsN], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>]>, + // + // Single-precision FP Store + // use FU_Issue to enforce the 1 load/store per cycle limit + InstrItinData<IIC_fpStore32,[InstrStage<1, [FU_DRegsVFP], 0, Required>, + InstrStage<2, [FU_DRegsN], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>]>, + // + // Double-precision FP Store + // use FU_Issue to enforce the 1 load/store per cycle limit + InstrItinData<IIC_fpStore64,[InstrStage<1, [FU_DRegsVFP], 0, Required>, + InstrStage<2, [FU_DRegsN], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>]>, + // + // FP Store Multiple + // use FU_Issue to enforce the 1 load/store per cycle limit + InstrItinData<IIC_fpStorem, [InstrStage<1, [FU_DRegsVFP], 0, Required>, + InstrStage<2, [FU_DRegsN], 0, Reserved>, + InstrStage<1, [FU_Issue], 0>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_LdSt0], 0>, + InstrStage<1, [FU_NPipe]>]>, // NEON // Issue through integer pipeline, and execute in NEON unit. // FIXME: Neon pipeline and LdSt unit are multiplexed. |