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author | Evan Cheng <evan.cheng@apple.com> | 2009-07-11 01:06:50 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2009-07-11 01:06:50 +0000 |
commit | 8955e93b1ffa7645beea0b51e4b091b96063f613 (patch) | |
tree | b5210193552097fd69cb7f865cfb68d59f0f6889 | |
parent | aad3460086a1b29c55f7490c6d8743ea4e53f07d (diff) | |
download | external_llvm-8955e93b1ffa7645beea0b51e4b091b96063f613.zip external_llvm-8955e93b1ffa7645beea0b51e4b091b96063f613.tar.gz external_llvm-8955e93b1ffa7645beea0b51e4b091b96063f613.tar.bz2 |
Fix up support for OptionalDefOperand when it defaults to an actual register def. I need this to get ready for major Thumb1 surgery.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75328 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp index 7926339..f9bfe00 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp @@ -160,8 +160,15 @@ void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, // register instead of creating a new vreg. unsigned VRBase = 0; const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, II, i); + if (II.OpInfo[i].isOptionalDef()) { + // Optional def must be a physical register. + unsigned NumResults = CountResults(Node); + VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); + assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); + MI->addOperand(MachineOperand::CreateReg(VRBase, true)); + } - if (!IsClone && !IsCloned) + if (!VRBase && !IsClone && !IsCloned) for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); UI != E; ++UI) { SDNode *User = *UI; @@ -507,12 +514,17 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned, // Emit all of the actual operands of this instruction, adding them to the // instruction as appropriate. - for (unsigned i = 0; i != NodeOperands; ++i) - AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap); + bool HasOptPRefs = II.getNumDefs() > NumResults; + assert((!HasOptPRefs || !HasPhysRegOuts) && + "Unable to cope with optional defs and phys regs defs!"); + unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; + for (unsigned i = NumSkip; i != NodeOperands; ++i) + AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, + VRBaseMap); // Emit all of the memory operands of this instruction for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i) - AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO); + AddMemOperand(MI,cast<MemOperandSDNode>(Node->getOperand(i+NumSkip))->MO); if (II.usesCustomDAGSchedInsertionHook()) { // Insert this instruction into the basic block using a target |