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author | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-14 01:15:52 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-14 01:15:52 +0000 |
commit | 899ee589f5182a35495f068ae15b5f2b5ff4ef8a (patch) | |
tree | 20318e40861a533953b6570e492d9f9c3cbcb480 | |
parent | 88373c29fe9d0b498ed21c3d29129f31806d7ec8 (diff) | |
download | external_llvm-899ee589f5182a35495f068ae15b5f2b5ff4ef8a.zip external_llvm-899ee589f5182a35495f068ae15b5f2b5ff4ef8a.tar.gz external_llvm-899ee589f5182a35495f068ae15b5f2b5ff4ef8a.tar.bz2 |
[mips] Fix bug in parsing accumulator registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188344 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 4 | ||||
-rw-r--r-- | test/MC/Mips/mips-dsp-instructions.s | 14 |
2 files changed, 16 insertions, 2 deletions
diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 28ad090..c9bc29a 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -861,8 +861,8 @@ int MipsAsmParser::matchFCCRegisterName(StringRef Name) { int MipsAsmParser::matchACRegisterName(StringRef Name) { - if (Name.startswith("acc")) { - StringRef NumString = Name.substr(3); + if (Name.startswith("ac")) { + StringRef NumString = Name.substr(2); unsigned IntVal; if (NumString.getAsInteger(10, IntVal)) return -1; // This is not an integer. diff --git a/test/MC/Mips/mips-dsp-instructions.s b/test/MC/Mips/mips-dsp-instructions.s index 4de88ce..50762bc 100644 --- a/test/MC/Mips/mips-dsp-instructions.s +++ b/test/MC/Mips/mips-dsp-instructions.s @@ -22,6 +22,13 @@ # CHECK: precr_sra_r.ph.w $25, $26, 0 # encoding: [0x7f,0x59,0x07,0xd1] # CHECK: precr_sra_r.ph.w $25, $26, 31 # encoding: [0x7f,0x59,0xff,0xd1] +# CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x43,0x18,0x18] +# CHECK: multu $ac2, $4, $5 # encoding: [0x00,0x85,0x10,0x19] +# CHECK: madd $ac1, $6, $7 # encoding: [0x70,0xc7,0x08,0x00] +# CHECK: maddu $ac0, $8, $9 # encoding: [0x71,0x09,0x00,0x01] +# CHECK: msub $ac3, $10, $11 # encoding: [0x71,0x4b,0x18,0x04] +# CHECK: msubu $ac2, $12, $13 # encoding: [0x71,0x8d,0x10,0x05] + precrq.qb.ph $16,$17,$18 precrq.ph.w $17,$18,$19 precrq_rs.ph.w $18,$19,$20 @@ -42,3 +49,10 @@ precr_sra.ph.w $24,$25,31 precr_sra_r.ph.w $25,$26,0 precr_sra_r.ph.w $25,$26,31 + + mult $ac3, $2, $3 + multu $ac2, $4, $5 + madd $ac1, $6, $7 + maddu $ac0, $8, $9 + msub $ac3, $10, $11 + msubu $ac2, $12, $13 |