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author | Jyotsna Verma <jverma@codeaurora.org> | 2013-05-07 15:06:29 +0000 |
---|---|---|
committer | Jyotsna Verma <jverma@codeaurora.org> | 2013-05-07 15:06:29 +0000 |
commit | 8cc93593cdfaa02f661c2bed96b7893c4f250b1e (patch) | |
tree | de4bc8b55c9931006285d246b70cc6648f5a9c1c | |
parent | c208c43a8ac5bfd3ee09b048cbc3f760691cefad (diff) | |
download | external_llvm-8cc93593cdfaa02f661c2bed96b7893c4f250b1e.zip external_llvm-8cc93593cdfaa02f661c2bed96b7893c4f250b1e.tar.gz external_llvm-8cc93593cdfaa02f661c2bed96b7893c4f250b1e.tar.bz2 |
Hexagon: Set accessSize and addrMode on all load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181324 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Hexagon/HexagonInstrFormats.td | 1 | ||||
-rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfo.td | 99 | ||||
-rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfoV4.td | 90 | ||||
-rw-r--r-- | lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h | 3 |
4 files changed, 125 insertions, 68 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td index 587fa7d..f97143f 100644 --- a/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/lib/Target/Hexagon/HexagonInstrFormats.td @@ -54,6 +54,7 @@ def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode def BaseImmOffset : AddrModeType<3>; // Indirect with offset def BaseLongOffset : AddrModeType<4>; // Indirect with long offset def BaseRegOffset : AddrModeType<5>; // Indirect with register offset +def PostInc : AddrModeType<6>; // Post increment addressing mode class MemAccessSize<bits<3> value> { bits<3> Value = value; diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index 2a4b17b..d1e32c6 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -932,12 +932,21 @@ multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC, } let addrMode = BaseImmOffset, isMEMri = "true" in { - defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel; - defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel; - defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel; - defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel; - defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel; - defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel; + let accessSize = ByteAccess in { + defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel; + defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel; + } + + let accessSize = HalfWordAccess in { + defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel; + defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel; + } + + let accessSize = WordAccess in + defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel; + + let accessSize = DoubleWordAccess in + defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel; } def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)), @@ -1000,18 +1009,25 @@ multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC, } let addrMode = BaseImmOffset in { - defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, - 11, 6>, AddrModeRel; - defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext, - 11, 6>, AddrModeRel; - defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, - 12, 7>, AddrModeRel; - defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, - 12, 7>, AddrModeRel; - defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, - 13, 8>, AddrModeRel; - defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, - 14, 9>, AddrModeRel; + let accessSize = ByteAccess in { + defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, + 11, 6>, AddrModeRel; + defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext, + 11, 6>, AddrModeRel; + } + let accessSize = HalfWordAccess in { + defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, + 12, 7>, AddrModeRel; + defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, + 12, 7>, AddrModeRel; + } + let accessSize = WordAccess in + defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, + 13, 8>, AddrModeRel; + + let accessSize = DoubleWordAccess in + defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, + 14, 9>, AddrModeRel; } let AddedComplexity = 20 in { @@ -1036,8 +1052,6 @@ def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))), //===----------------------------------------------------------------------===// // Post increment load -// Make sure that in post increment load, the first operand is always the post -// increment operand. //===----------------------------------------------------------------------===// multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp, @@ -1079,7 +1093,7 @@ multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC, } } -let hasCtrlDep = 1, neverHasSideEffects = 1 in { +let hasCtrlDep = 1, neverHasSideEffects = 1, addrMode = PostInc in { defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>, PredNewRel; defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>, @@ -1382,7 +1396,7 @@ multiclass ST_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp, multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC, Operand ImmOp, bit PredNot> { let isPredicatedFalse = PredNot in { - defm _c#NAME# : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>; + defm _c#NAME : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>; // Predicate new let Predicates = [HasV4T], validSubTargets = HasV4SubT in defm _cdn#NAME#_V4 : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>; @@ -1397,7 +1411,7 @@ multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC, let isPredicable = 1 in def NAME : STInst2PI<(outs IntRegs:$dst), (ins IntRegs:$src1, ImmOp:$offset, RC:$src2), - #mnemonic#"($src1++#$offset) = $src2", + mnemonic#"($src1++#$offset) = $src2", [], "$src1 = $dst">; @@ -1474,12 +1488,17 @@ multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC, } let addrMode = BaseImmOffset, isMEMri = "true" in { - defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel; - defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel; - defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel; + let accessSize = ByteAccess in + defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel; + + let accessSize = HalfWordAccess in + defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel; + + let accessSize = WordAccess in + defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel; - let isNVStorable = 0 in - defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel; + let accessSize = DoubleWordAccess, isNVStorable = 0 in + defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel; } def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr), @@ -1541,15 +1560,21 @@ multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC, } let addrMode = BaseImmOffset, InputType = "reg" in { - defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, - u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel; - defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, - u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel; - defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, - u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel; - let isNVStorable = 0 in - defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext, - u6_3Ext, 14, 9>, AddrModeRel; + let accessSize = ByteAccess in + defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, + u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel; + + let accessSize = HalfWordAccess in + defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, + u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel; + + let accessSize = WordAccess in + defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, + u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel; + + let accessSize = DoubleWordAccess, isNVStorable = 0 in + defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext, + u6_3Ext, 14, 9>, AddrModeRel; } let AddedComplexity = 10 in { diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index 933239d..c7f4edf 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -213,7 +213,7 @@ def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst), // Template class for load instructions with Absolute set addressing mode. //===----------------------------------------------------------------------===// let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1, -validSubTargets = HasV4SubT in +validSubTargets = HasV4SubT, addrMode = AbsoluteSet in class T_LD_abs_set<string mnemonic, RegisterClass RC>: LDInst2<(outs RC:$dst1, IntRegs:$dst2), (ins u0AlwaysExt:$addr), @@ -266,12 +266,23 @@ multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> { } let addrMode = BaseRegOffset in { - defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel; - defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel; - defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel; - defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel; - defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel; - defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel; + let accessSize = ByteAccess in { + defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, + AddrModeRel; + defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, + AddrModeRel; + } + let accessSize = HalfWordAccess in { + defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel; + defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, + AddrModeRel; + } + let accessSize = WordAccess in + defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel; + + let accessSize = DoubleWordAccess in + defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, + AddrModeRel; } // 'def pats' for load instructions with base + register offset and non-zero @@ -456,7 +467,8 @@ def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))), //===----------------------------------------------------------------------===// // Template class for store instructions with Absolute set addressing mode. //===----------------------------------------------------------------------===// -let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in +let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT, +addrMode = AbsoluteSet in class T_ST_abs_set<string mnemonic, RegisterClass RC>: STInst2<(outs IntRegs:$dst1), (ins RC:$src1, u0AlwaysExt:$src2), @@ -551,17 +563,20 @@ multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> { let addrMode = BaseRegOffset, neverHasSideEffects = 1, validSubTargets = HasV4SubT in { - defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>, - ST_Idxd_shl_nv<"memb", "STrib", IntRegs>, AddrModeRel; + let accessSize = ByteAccess in + defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>, + ST_Idxd_shl_nv<"memb", "STrib", IntRegs>, AddrModeRel; - defm STrih_indexed_shl: ST_Idxd_shl<"memh", "STrih", IntRegs>, - ST_Idxd_shl_nv<"memh", "STrih", IntRegs>, AddrModeRel; + let accessSize = HalfWordAccess in + defm STrih_indexed_shl: ST_Idxd_shl<"memh", "STrih", IntRegs>, + ST_Idxd_shl_nv<"memh", "STrih", IntRegs>, AddrModeRel; - defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>, - ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel; + let accessSize = WordAccess in + defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>, + ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel; - let isNVStorable = 0 in - defm STrid_indexed_shl: ST_Idxd_shl<"memd", "STrid", DoubleRegs>, AddrModeRel; + let isNVStorable = 0, accessSize = DoubleWordAccess in + defm STrid_indexed_shl: ST_Idxd_shl<"memd", "STrid", DoubleRegs>, AddrModeRel; } let Predicates = [HasV4T], AddedComplexity = 10 in { @@ -695,10 +710,15 @@ multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> { } let addrMode = BaseImmOffset, InputType = "imm", - validSubTargets = HasV4SubT in { - defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel, PredNewRel; - defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel, PredNewRel; - defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel, PredNewRel; +validSubTargets = HasV4SubT in { + let accessSize = ByteAccess in + defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel, PredNewRel; + + let accessSize = HalfWordAccess in + defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel, PredNewRel; + + let accessSize = WordAccess in + defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel, PredNewRel; } let Predicates = [HasV4T], AddedComplexity = 10 in { @@ -834,12 +854,17 @@ multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC, } let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in { - defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext, - u6_0Ext, 11, 6>, AddrModeRel; - defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext, - u6_1Ext, 12, 7>, AddrModeRel; - defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext, - u6_2Ext, 13, 8>, AddrModeRel; + let accessSize = ByteAccess in + defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext, + u6_0Ext, 11, 6>, AddrModeRel; + + let accessSize = HalfWordAccess in + defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext, + u6_1Ext, 12, 7>, AddrModeRel; + + let accessSize = WordAccess in + defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext, + u6_2Ext, 13, 8>, AddrModeRel; } // multiclass for new-value store instructions with base + immediate offset. @@ -887,9 +912,14 @@ multiclass ST_MEMri_nv<string mnemonic, string CextOp, RegisterClass RC, let addrMode = BaseImmOffset, isMEMri = "true", validSubTargets = HasV4SubT, mayStore = 1 in { - defm STrib: ST_MEMri_nv<"memb", "STrib", IntRegs, 11, 6>, AddrModeRel; - defm STrih: ST_MEMri_nv<"memh", "STrih", IntRegs, 12, 7>, AddrModeRel; - defm STriw: ST_MEMri_nv<"memw", "STriw", IntRegs, 13, 8>, AddrModeRel; + let accessSize = ByteAccess in + defm STrib: ST_MEMri_nv<"memb", "STrib", IntRegs, 11, 6>, AddrModeRel; + + let accessSize = HalfWordAccess in + defm STrih: ST_MEMri_nv<"memh", "STrih", IntRegs, 12, 7>, AddrModeRel; + + let accessSize = WordAccess in + defm STriw: ST_MEMri_nv<"memw", "STriw", IntRegs, 13, 8>, AddrModeRel; } //===----------------------------------------------------------------------===// @@ -939,7 +969,7 @@ multiclass ST_PostInc_nv<string mnemonic, string BaseOp, RegisterClass RC, } } -let validSubTargets = HasV4SubT in { +let addrMode = PostInc, validSubTargets = HasV4SubT in { defm POST_STbri: ST_PostInc_nv <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel; defm POST_SThri: ST_PostInc_nv <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel; defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel; diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index d4a93b5..e0f5a27 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -65,7 +65,8 @@ namespace HexagonII { AbsoluteSet = 2, // Absolute set addressing mode BaseImmOffset = 3, // Indirect with offset BaseLongOffset = 4, // Indirect with long offset - BaseRegOffset = 5 // Indirect with register offset + BaseRegOffset = 5, // Indirect with register offset + PostInc = 6 // Post increment addressing mode }; enum MemAccessSize { |