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| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-02-19 20:16:45 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-02-19 20:16:45 +0000 |
| commit | 909a0e0e95e2b96f5d07d40fb53c5892bea20f83 (patch) | |
| tree | 789024f955c9a6a641e9fb7af65ac3e28e4a1d8c | |
| parent | 03544ec2a43fab162d25cf44627d1d08430bcccd (diff) | |
| download | external_llvm-909a0e0e95e2b96f5d07d40fb53c5892bea20f83.zip external_llvm-909a0e0e95e2b96f5d07d40fb53c5892bea20f83.tar.gz external_llvm-909a0e0e95e2b96f5d07d40fb53c5892bea20f83.tar.bz2 | |
ARM NEON: Don't need COPY_TO_REGCLASS in pattern
In my previous commit:
"Merge a f32 bitcast of a v2i32 extractelt
A vectorized sitfp on doubles will get scalarized to a sequence of an
extract_element of <2 x i32>, a bitcast to f32 and a sitofp.
Due to the the extract_element, and the bitcast we will uneccessarily generate
moves between scalar and vector registers."
I added a pattern containing a copy_to_regclass. The copy_to_regclass is
actually not needed.
radar://13191881
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175555 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 9f68c22..0411ac4 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -5747,9 +5747,7 @@ def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>; // Fold extracting an element out of a v2i32 into a vfp register. def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))), - (f32 (EXTRACT_SUBREG - (v2f32 (COPY_TO_REGCLASS (v2i32 DPR:$src), DPR)), - (SSubReg_f32_reg imm:$lane)))>; + (f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>; // Vector lengthening move with load, matching extending loads. |