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authorJim Grosbach <grosbach@apple.com>2010-12-10 21:05:07 +0000
committerJim Grosbach <grosbach@apple.com>2010-12-10 21:05:07 +0000
commit90cc533fda9742f5c67203f97e69e5efd270c676 (patch)
tree5709105b49bf8007daa70ac6d9024b5e3c922b30
parent683fc3e9afeda5178ab0644f4ba299715f53a7c8 (diff)
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Fix encoding of 'U' bit for Thumb2 STRD/LDRD instructions. rdar://8755726
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121524 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMMCCodeEmitter.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index bf869f7..df28a99 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -552,9 +552,9 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
uint32_t ARMMCCodeEmitter::
getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
- // {17-13} = reg
- // {12} = (U)nsigned (add == '1', sub == '0')
- // {11-0} = imm8
+ // {12-9} = reg
+ // {8} = (U)nsigned (add == '1', sub == '0')
+ // {7-0} = imm8
unsigned Reg, Imm8;
bool isAdd = true;
// If The first operand isn't a register, we have a label reference.
@@ -576,7 +576,7 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
uint32_t Binary = (Imm8 >> 2) & 0xff;
// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
if (isAdd)
- Binary |= (1 << 9);
+ Binary |= (1 << 8);
Binary |= (Reg << 9);
return Binary;
}