Improved asm inline for hi,lo results

Added hi,lo registers to be used,def implicitly. This provides better handle of
instructions which use hi/lo.
Fixes a small BranchAnalysis bug


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54274 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 77 insertions, 23 deletions

diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp
index 9e334c1..d53fd06 100644
--- a/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -59,6 +59,8 @@ namespace {
     }
 
     virtual std::string getSectionForFunction(const Function &F) const;
+    bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, 
+                         unsigned AsmVariant, const char *ExtraCode);
     void printOperand(const MachineInstr *MI, int opNum);
     void printMemOperand(const MachineInstr *MI, int opNum, 
                          const char *Modifier = 0);
@@ -337,6 +339,19 @@ runOnMachineFunction(MachineFunction &MF)
   return false;
 }
 
+// Print out an operand for an inline asm expression.
+bool MipsAsmPrinter::
+PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, 
+                unsigned AsmVariant, const char *ExtraCode) 
+{
+  // Does this asm operand have a single letter operand modifier?
+  if (ExtraCode && ExtraCode[0]) 
+    return true; // Unknown modifier.
+
+  printOperand(MI, OpNo);
+  return false;
+}
+
 void MipsAsmPrinter::
 printOperand(const MachineInstr *MI, int opNum) 
 {
diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index ccd846e..6bbf240 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -11,7 +11,6 @@
 //
 //===----------------------------------------------------------------------===//
 
-//#include "Mips.h"
 #include "MipsInstrInfo.h"
 #include "MipsTargetMachine.h"
 #include "llvm/ADT/STLExtras.h"
@@ -101,11 +100,11 @@ isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const
 {
   if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
       (MI->getOpcode() == Mips::SWC1A) || (MI->getOpcode() == Mips::SDC1)) {
-    if ((MI->getOperand(0).isFrameIndex()) && // is a stack slot
+    if ((MI->getOperand(2).isFrameIndex()) && // is a stack slot
         (MI->getOperand(1).isImmediate()) &&  // the imm is zero
         (isZeroImm(MI->getOperand(1)))) {
-      FrameIndex = MI->getOperand(0).getIndex();
-      return MI->getOperand(2).getReg();
+      FrameIndex = MI->getOperand(2).getIndex();
+      return MI->getOperand(0).getReg();
     }
   }
   return 0;
@@ -137,14 +136,27 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
     else if ((DestRC == Mips::AFGR32RegisterClass) &&
              (SrcRC == Mips::CPURegsRegisterClass))
       BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg);
+    else if ((DestRC == Mips::AFGR32RegisterClass) &&
+             (SrcRC == Mips::CPURegsRegisterClass))
+      BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg);
     else if ((SrcRC == Mips::CCRRegisterClass) && 
              (SrcReg == Mips::FCR31))
       return; // This register is used implicitly, no copy needed.
     else if ((DestRC == Mips::CCRRegisterClass) && 
              (DestReg == Mips::FCR31))
       return; // This register is used implicitly, no copy needed.
-    else
+    else if ((DestRC == Mips::HILORegisterClass) &&
+             (SrcRC == Mips::CPURegsRegisterClass)) {
+      unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
+      BuildMI(MBB, I, get(Opc), DestReg);
+    } else if ((SrcRC == Mips::HILORegisterClass) &&
+               (DestRC == Mips::CPURegsRegisterClass)) {
+      unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
+      BuildMI(MBB, I, get(Opc), DestReg);
+    } else
       assert (0 && "DestRC != SrcRC, Can't copy this register");
+
+    return;
   }
 
   if (DestRC == Mips::CPURegsRegisterClass)
@@ -280,8 +292,8 @@ foldMemoryOperand(MachineFunction &MF,
       if (Ops[0] == 0) {    // COPY -> STORE
         unsigned SrcReg = MI->getOperand(2).getReg();
         bool isKill = MI->getOperand(2).isKill();
-        NewMI = BuildMI(MF, get(Mips::SW)).addFrameIndex(FI)
-          .addImm(0).addReg(SrcReg, false, false, isKill);
+        NewMI = BuildMI(MF, get(Mips::SW)).addReg(SrcReg, false, false, isKill)
+          .addImm(0).addFrameIndex(FI);
       } else {              // COPY -> LOAD
         unsigned DstReg = MI->getOperand(0).getReg();
         bool isDead = MI->getOperand(0).isDead();
@@ -312,8 +324,8 @@ foldMemoryOperand(MachineFunction &MF,
       if (Ops[0] == 0) {    // COPY -> STORE
         unsigned SrcReg = MI->getOperand(1).getReg();
         bool isKill = MI->getOperand(1).isKill();
-        NewMI = BuildMI(MF, get(StoreOpc)).addFrameIndex(FI)
-          .addImm(0).addReg(SrcReg, false, false, isKill);
+        NewMI = BuildMI(MF, get(StoreOpc)).addReg(SrcReg, false, false, isKill)
+          .addImm(0).addFrameIndex(FI) ;
       } else {              // COPY -> LOAD
         unsigned DstReg = MI->getOperand(0).getReg();
         bool isDead = MI->getOperand(0).isDead();
@@ -487,7 +499,7 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
   unsigned SecondLastOpc    = SecondLastInst->getOpcode();
   Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
 
-  if (SecondLastOpc != Mips::COND_INVALID && LastOpc == Mips::J) {
+  if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
     int SecondNumOp = SecondLastInst->getNumOperands();
 
     TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
@@ -584,7 +596,7 @@ RemoveBranch(MachineBasicBlock &MBB) const
   return 2;
 }
 
-/// BlockHasNoFallThrough - Analyse if MachineBasicBlock does not
+/// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
 /// fall-through into its successor block.
 bool MipsInstrInfo::
 BlockHasNoFallThrough(MachineBasicBlock &MBB) const 
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 9b1b930..ddf18d8 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -315,7 +315,7 @@ class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
       [], itin>;
 
 // Move from Hi/Lo
-class MoveFromTo<bits<6> func, string instr_asm>:
+class MoveFromLOHI<bits<6> func, string instr_asm>:
   FR< 0x00,
       func,
       (outs CPURegs:$dst),
@@ -323,6 +323,14 @@ class MoveFromTo<bits<6> func, string instr_asm>:
       !strconcat(instr_asm, "\t$dst"),
       [], IIHiLo>;
 
+class MoveToLOHI<bits<6> func, string instr_asm>:
+  FR< 0x00,
+      func,
+      (outs),
+      (ins CPURegs:$src),
+      !strconcat(instr_asm, "\t$src"),
+      [], IIHiLo>;
+
 // Count Leading Ones/Zeros in Word
 class CountLeading<bits<6> func, string instr_asm>:
   FR< 0x1c,
@@ -459,14 +467,22 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1,
                 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
 
 /// Multiply and Divide Instructions. 
-def MULT    : MulDiv<0x18, "mult", IIImul>;
-def MULTu   : MulDiv<0x19, "multu", IIImul>;
-def DIV     : MulDiv<0x1a, "div", IIIdiv>;
-def DIVu    : MulDiv<0x1b, "divu", IIIdiv>;
-def MFHI    : MoveFromTo<0x10, "mfhi">;
-def MFLO    : MoveFromTo<0x12, "mflo">;
-def MTHI    : MoveFromTo<0x11, "mthi">;
-def MTLO    : MoveFromTo<0x13, "mtlo">;
+let Defs = [HI, LO] in {
+  def MULT    : MulDiv<0x18, "mult", IIImul>;
+  def MULTu   : MulDiv<0x19, "multu", IIImul>;
+  def DIV     : MulDiv<0x1a, "div", IIIdiv>;
+  def DIVu    : MulDiv<0x1b, "divu", IIIdiv>;
+}
+
+let Defs = [HI] in
+  def MTHI  : MoveToLOHI<0x11, "mthi">;
+let Defs = [LO] in
+  def MTLO  : MoveToLOHI<0x13, "mtlo">;
+
+let Uses = [HI] in
+  def MFHI  : MoveFromLOHI<0x10, "mfhi">;
+let Uses = [LO] in
+  def MFLO  : MoveFromLOHI<0x12, "mflo">;
 
 /// Sign Ext In Register Instructions.
 let Predicates = [HasSEInReg] in {
diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp
index 2c92060..c25bd1e 100644
--- a/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -217,14 +217,17 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
            "Instr doesn't have FrameIndex operand!");
   }
 
+  #ifndef NDEBUG
+  DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
+  DOUT << "<--------->\n";
+  MI.print(DOUT);
+  #endif
+
   int FrameIndex = MI.getOperand(i).getIndex();
   int stackSize  = MF.getFrameInfo()->getStackSize();
   int spOffset   = MF.getFrameInfo()->getObjectOffset(FrameIndex);
 
   #ifndef NDEBUG
-  DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
-  DOUT << "<--------->\n";
-  MI.print(DOUT);
   DOUT << "FrameIndex : " << FrameIndex << "\n";
   DOUT << "spOffset   : " << spOffset << "\n";
   DOUT << "stackSize  : " << stackSize << "\n";
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index 0a7a69e..10956aa 100644
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -126,6 +126,10 @@ let Namespace = "Mips" in {
   def D14 : AFPR<28, "F28", [F28, F29]>, DwarfRegNum<[60]>;
   def D15 : AFPR<30, "F30", [F30, F31]>, DwarfRegNum<[62]>;
 
+  // Hi/Lo registers
+  def HI  : Register<"hi">, DwarfRegNum<[64]>;
+  def LO  : Register<"lo">, DwarfRegNum<[65]>;
+
   // Status flags register
   def FCR31 : Register<"FCR31">;
 }
@@ -233,3 +237,7 @@ def CCR : RegisterClass<"Mips", [i32], 32, [FCR31]> {
   let CopyCost = -1;  // Don't allow copying of status registers.
 }
 
+def HILO : RegisterClass<"Mips", [i32], 32, [HI, LO]> {
+  //let CopyCost = -1;  // Don't allow copying of hi/lo registers.
+}
+