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| author | Hal Finkel <hfinkel@anl.gov> | 2013-07-08 20:00:03 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-07-08 20:00:03 +0000 |
| commit | 947d447ee0ac927cc308e5e53062e0edb71e7d8e (patch) | |
| tree | 4996eef8eb05328fbde96de76692061b0ae374c4 | |
| parent | e5a532dae346f5f34d8ae8fa3f8f0ff3c747243e (diff) | |
| download | external_llvm-947d447ee0ac927cc308e5e53062e0edb71e7d8e.zip external_llvm-947d447ee0ac927cc308e5e53062e0edb71e7d8e.tar.gz external_llvm-947d447ee0ac927cc308e5e53062e0edb71e7d8e.tar.bz2 | |
PPC: Mark vector CC action for SETO and SETONE as Expand
Another bug found by llvm-stress! This fixes hitting
llvm_unreachable("Invalid integer vector compare condition");
at the end of getVCmpInst in PPCISelDAGToDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185855 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 3 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/altivec-ord.ll | 17 |
2 files changed, 20 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 685b082..1759c04 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -487,6 +487,9 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand); setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand); setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand); + + setCondCodeAction(ISD::SETO, MVT::v4f32, Expand); + setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand); } if (Subtarget->has64BitSupport()) { diff --git a/test/CodeGen/PowerPC/altivec-ord.ll b/test/CodeGen/PowerPC/altivec-ord.ll new file mode 100644 index 0000000..6aea843 --- /dev/null +++ b/test/CodeGen/PowerPC/altivec-ord.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define <4 x i16> @test(<4 x float> %f, <4 x float> %g) { +entry: + %r = fcmp ord <4 x float> %f, %g + %s = sext <4 x i1> %r to <4 x i16> + ret <4 x i16> %s +} + +define <4 x i16> @test2(<4 x float> %f, <4 x float> %g) { +entry: + %r = fcmp one <4 x float> %f, %g + %s = sext <4 x i1> %r to <4 x i16> + ret <4 x i16> %s +} + |