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authorAlkis Evlogimenos <alkis@evlogimenos.com>2004-02-29 18:44:03 +0000
committerAlkis Evlogimenos <alkis@evlogimenos.com>2004-02-29 18:44:03 +0000
commit96c9b8b49691c715ccc848ea3ef941f6e9b7e8f2 (patch)
treec9400954c97d4d27c245b1551b9fdf2b17daf6d8
parent7f6124cfc29e1559759e51737535b2fe6257a788 (diff)
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Add instruction name description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11998 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/README.txt21
1 files changed, 19 insertions, 2 deletions
diff --git a/lib/Target/X86/README.txt b/lib/Target/X86/README.txt
index 643559a..46849af 100644
--- a/lib/Target/X86/README.txt
+++ b/lib/Target/X86/README.txt
@@ -66,7 +66,7 @@ and the third is the second source register (#1025). Never forget the
destination register will show up in the MachineInstr operands vector. The code
to generate this instruction looks like this:
- BuildMI(BB, X86::ADDrr32, 2, 1027).addReg(1026).addReg(1025);
+ BuildMI(BB, X86::ADD32rr, 2, 1027).addReg(1026).addReg(1025);
The first argument to BuildMI is the basic block to append the machine
instruction to, the second is the opcode, the third is the number of operands,
@@ -149,8 +149,25 @@ Stores and all other instructions treat the four memory operands in the same
way, in the same order.
+======================
+VI. Instruction naming
+======================
+
+An instruction name consists of the base name, a default operand size
+followed by a character per operand with an optional special size. For
+example:
+
+ADD8rr -> add, 8-bit register, 8-bit register
+
+IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate
+
+IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate
+
+MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
+
+
==========================
-VI. TODO / Future Projects
+VII. TODO / Future Projects
==========================
Ideas for Improvements: