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| author | Duncan Sands <baldrick@free.fr> | 2010-06-29 13:00:29 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2010-06-29 13:00:29 +0000 |
| commit | 978189e090e809c1a6efcf2677e785a06f71029e (patch) | |
| tree | 961ea6a5d48b34b6a6f6faeaf059df8aeda62271 | |
| parent | 78337b4d4d848c85a70d7977bd889317bd830dc7 (diff) | |
| download | external_llvm-978189e090e809c1a6efcf2677e785a06f71029e.zip external_llvm-978189e090e809c1a6efcf2677e785a06f71029e.tar.gz external_llvm-978189e090e809c1a6efcf2677e785a06f71029e.tar.bz2 | |
Remove an unused and a pointless variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107131 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 35a983e..3bddca0 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -533,7 +533,6 @@ bool ARMDAGToDAGISel::SelectAddrModePC(SDNode *Op, SDValue N, bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDNode *Op, SDValue N, SDValue &Base, SDValue &Offset){ // FIXME dl should come from the parent load or store, not the address - DebugLoc dl = Op->getDebugLoc(); if (N.getOpcode() != ISD::ADD) { ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N); if (!NC || !NC->isNullValue()) @@ -1382,13 +1381,11 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, // Quad registers are handled by load/store of subregs. Find the subreg info. unsigned NumElts = 0; - int SubregIdx = 0; bool Even = false; EVT RegVT = VT; if (!is64BitVector) { RegVT = GetNEONSubregVT(VT); NumElts = RegVT.getVectorNumElements(); - SubregIdx = (Lane < NumElts) ? ARM::dsub_0 : ARM::dsub_1; Even = Lane < NumElts; } |