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| author | Chris Lattner <sabre@nondot.org> | 2010-08-26 05:24:29 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-08-26 05:24:29 +0000 |
| commit | 97a2a56f433b35ab60431e7681cf1b5c97c71529 (patch) | |
| tree | 5a1e679e916c877c72a203bcda1fb81fc874e471 | |
| parent | 076137c424bfae2c28e45121b1468397a7d2712a (diff) | |
| download | external_llvm-97a2a56f433b35ab60431e7681cf1b5c97c71529.zip external_llvm-97a2a56f433b35ab60431e7681cf1b5c97c71529.tar.gz external_llvm-97a2a56f433b35ab60431e7681cf1b5c97c71529.tar.bz2 | |
fix sse1 only codegen in x86-64 mode, which is something we
apparently try to support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112168 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 17 | ||||
| -rw-r--r-- | test/CodeGen/X86/sse1.ll | 7 |
2 files changed, 18 insertions, 6 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index ad43175..c2e37b6 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1342,12 +1342,18 @@ X86TargetLowering::LowerReturn(SDValue Chain, if (Subtarget->is64Bit()) { if (ValVT.isVector() && ValVT.getSizeInBits() == 64) { ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy); - if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) + if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy); + + // If we don't have SSE2 available, convert to v4f32 so the generated + // register is legal. + if (!Subtarget->hasSSE2()) + ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,ValToCopy); + } } } - + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); Flag = Chain.getValue(1); } @@ -3931,10 +3937,9 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { } } - if (NumNonZero == 0) { - // All undef vector. Return an UNDEF. All zero vectors were handled above. + // All undef vector. Return an UNDEF. All zero vectors were handled above. + if (NumNonZero == 0) return DAG.getUNDEF(VT); - } // Special case for single non-zero, non-undef, element. if (NumNonZero == 1) { @@ -4072,7 +4077,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { if (EVTBits == 16 && NumElems == 8) { SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, - *this); + *this); if (V.getNode()) return V; } diff --git a/test/CodeGen/X86/sse1.ll b/test/CodeGen/X86/sse1.ll new file mode 100644 index 0000000..2c1acb6 --- /dev/null +++ b/test/CodeGen/X86/sse1.ll @@ -0,0 +1,7 @@ +; Tests for SSE1 and below, without SSE2+. +; RUN: llc < %s -mcpu=pentium3 -O3 | FileCheck %s + +define <8 x i16> @test1(<8 x i32> %a) nounwind { +; CHECK: test1 + ret <8 x i16> zeroinitializer +} |