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author | Evan Cheng <evan.cheng@apple.com> | 2009-12-15 00:41:36 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2009-12-15 00:41:36 +0000 |
commit | 99b653c36f0141f6b9515d688960ac8c2cb857ff (patch) | |
tree | bd6bd822b11a900dd8d14baed63cb4dea752bd4e | |
parent | 0c479d3c6bd474e5135bddfed42f37e3092cac31 (diff) | |
download | external_llvm-99b653c36f0141f6b9515d688960ac8c2cb857ff.zip external_llvm-99b653c36f0141f6b9515d688960ac8c2cb857ff.tar.gz external_llvm-99b653c36f0141f6b9515d688960ac8c2cb857ff.tar.bz2 |
Propagate zest through logical shift.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91378 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 10 | ||||
-rw-r--r-- | test/CodeGen/X86/setcc.ll | 13 | ||||
-rw-r--r-- | test/CodeGen/X86/zext-shl.ll | 38 |
3 files changed, 61 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 027348c..52b7ed5 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3278,6 +3278,16 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { if (SCC.getNode()) return SCC; } + // (zext (shl (zext x), y)) -> (shl (zext x), (zext y)) + if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && + N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && + N0.hasOneUse()) { + DebugLoc dl = N->getDebugLoc(); + return DAG.getNode(N0.getOpcode(), dl, VT, + DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), + DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(1))); + } + return SDValue(); } diff --git a/test/CodeGen/X86/setcc.ll b/test/CodeGen/X86/setcc.ll new file mode 100644 index 0000000..785a6a9 --- /dev/null +++ b/test/CodeGen/X86/setcc.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s + +define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp { +entry: +; CHECK: t1: +; CHECK: seta %al +; CHECK: movzbl %al, %eax +; CHECK: shll $5, %eax + %0 = icmp ugt i16 %x, 26 ; <i1> [#uses=1] + %iftmp.1.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1] + ret i16 %iftmp.1.0 +} + diff --git a/test/CodeGen/X86/zext-shl.ll b/test/CodeGen/X86/zext-shl.ll new file mode 100644 index 0000000..bc3198a --- /dev/null +++ b/test/CodeGen/X86/zext-shl.ll @@ -0,0 +1,38 @@ +; RUN: llc < %s -march=x86 | FileCheck %s + +define i32 @t1(i8 zeroext %x) nounwind readnone ssp { +entry: +; CHECK: t1: +; CHECK: shll +; CHECK-NOT: movzwl +; CHECK: ret + %0 = zext i8 %x to i16 + %1 = shl i16 %0, 5 + %2 = zext i16 %1 to i32 + ret i32 %2 +} + +define i32 @t2(i8 zeroext %x) nounwind readnone ssp { +entry: +; CHECK: t2: +; CHECK: shrl +; CHECK-NOT: movzwl +; CHECK: ret + %0 = zext i8 %x to i16 + %1 = lshr i16 %0, 3 + %2 = zext i16 %1 to i32 + ret i32 %2 +} + +define i32 @t3(i8 zeroext %x, i8 zeroext %y) nounwind readnone ssp { +entry: +; CHECK: t3: +; CHECK: shll +; CHECK-NOT: movzwl +; CHECK: ret + %0 = zext i8 %x to i16 + %1 = zext i8 %y to i16 + %2 = shl i16 %0, %1 + %3 = zext i16 %2 to i32 + ret i32 %3 +} |