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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-07-22 19:30:38 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-07-22 19:30:38 +0000 |
| commit | 9a05b98ef9ec58c52f35ce04677f24ef62a79701 (patch) | |
| tree | bb57781a57ff97c48da73b224b5e0edd4c7f9e9b | |
| parent | 30115ec7a3e35038554d4131f3c515744cbdd933 (diff) | |
| download | external_llvm-9a05b98ef9ec58c52f35ce04677f24ef62a79701.zip external_llvm-9a05b98ef9ec58c52f35ce04677f24ef62a79701.tar.gz external_llvm-9a05b98ef9ec58c52f35ce04677f24ef62a79701.tar.bz2 | |
[mips] Fix MipsAsmParser::parseCCRRegs.
Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186861 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 27 | ||||
| -rw-r--r-- | test/MC/Mips/mips-fpu-instructions.s | 4 |
2 files changed, 13 insertions, 18 deletions
diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 56a5dfd..3e9b950 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1449,30 +1449,23 @@ MipsAsmParser::parseHW64Regs( MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { - unsigned RegNum; // If the first token is not '$' we have an error. if (Parser.getTok().isNot(AsmToken::Dollar)) - return MatchOperand_NoMatch; + return MatchOperand_ParseFail; + SMLoc S = Parser.getTok().getLoc(); Parser.Lex(); // Eat the '$' const AsmToken &Tok = Parser.getTok(); // Get next token. - if (Tok.is(AsmToken::Integer)) { - RegNum = Tok.getIntVal(); - // At the moment only fcc0 is supported. - if (RegNum != 0) - return MatchOperand_ParseFail; - } else if (Tok.is(AsmToken::Identifier)) { - // At the moment only fcc0 is supported. - if (Tok.getIdentifier() != "fcc0") - return MatchOperand_ParseFail; - } else - return MatchOperand_NoMatch; - MipsOperand *op = MipsOperand::CreateReg(Mips::FCC0, S, - Parser.getTok().getLoc()); - op->setRegKind(MipsOperand::Kind_CCRRegs); - Operands.push_back(op); + if (Tok.isNot(AsmToken::Integer)) + return MatchOperand_ParseFail; + + unsigned Reg = matchRegisterByNumber(Tok.getIntVal(), Mips::CCRRegClassID); + + MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc()); + Op->setRegKind(MipsOperand::Kind_CCRRegs); + Operands.push_back(Op); Parser.Lex(); // Eat the register number. return MatchOperand_Success; diff --git a/test/MC/Mips/mips-fpu-instructions.s b/test/MC/Mips/mips-fpu-instructions.s index 5ff31f3..256ce45 100644 --- a/test/MC/Mips/mips-fpu-instructions.s +++ b/test/MC/Mips/mips-fpu-instructions.s @@ -138,7 +138,8 @@ # FP move instructions #------------------------------------------------------------------------------ -# CHECK: cfc1 $6, $fcc0 # encoding: [0x00,0x00,0x46,0x44] +# CHECK: cfc1 $6, $0 # encoding: [0x00,0x00,0x46,0x44] +# CHECK: ctc1 $10, $31 # encoding: [0x00,0xf8,0xca,0x44] # CHECK: mfc1 $6, $f7 # encoding: [0x00,0x38,0x06,0x44] # CHECK: mfhi $5 # encoding: [0x10,0x28,0x00,0x00] # CHECK: mflo $5 # encoding: [0x12,0x28,0x00,0x00] @@ -162,6 +163,7 @@ # CHECK: suxc1 $f4, $24($5) # encoding: [0x0d,0x20,0xb8,0x4c] cfc1 $a2,$0 + ctc1 $10,$31 mfc1 $a2,$f7 mfhi $a1 mflo $a1 |