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authorRichard Osborne <richard@xmos.com>2013-01-27 20:46:21 +0000
committerRichard Osborne <richard@xmos.com>2013-01-27 20:46:21 +0000
commit9d2b1aef1b5bc8926c66b38f03583a77d015e921 (patch)
treebe278501e255bc40a23420b9637fd6cdb9a340dd
parentf5e7e793f196cfba4427321ee9f38ecc8bb8470f (diff)
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[XCore] Add missing 1r instructions.
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/XCore/XCoreInstrInfo.td27
-rw-r--r--test/MC/Disassembler/XCore/xcore.txt27
2 files changed, 48 insertions, 6 deletions
diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td
index 9ac9105..185083a 100644
--- a/lib/Target/XCore/XCoreInstrInfo.td
+++ b/lib/Target/XCore/XCoreInstrInfo.td
@@ -853,9 +853,6 @@ def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
[(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
// One operand short
-// TODO edu, eeu, waitet, waitef, tstart, clrtp
-// setdp, setcp, setev, kcall
-// dgetreg
def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),
"msync res[$a]",
[(int_xcore_msync GRRegs:$a)]>;
@@ -879,9 +876,13 @@ def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
[(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
let Defs=[SP], neverHasSideEffects=1 in
-def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a),
- "set sp, $a",
- []>;
+def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>;
+
+let neverHasSideEffects=1 in
+def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>;
+
+let neverHasSideEffects=1 in
+def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>;
let hasCtrlDep = 1 in
def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a),
@@ -919,10 +920,24 @@ def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a),
[(int_xcore_setev GRRegs:$a, R11)]>;
}
+def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>;
+
+def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", []>;
+
def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
"eeu res[$a]",
[(int_xcore_eeu GRRegs:$a)]>;
+def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>;
+
+def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>;
+
+def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>;
+
+def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>;
+
+def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]", []>;
+
// Zero operand short
def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
diff --git a/test/MC/Disassembler/XCore/xcore.txt b/test/MC/Disassembler/XCore/xcore.txt
index c620587..03b2c9a 100644
--- a/test/MC/Disassembler/XCore/xcore.txt
+++ b/test/MC/Disassembler/XCore/xcore.txt
@@ -110,6 +110,33 @@
# CHECK: eeu res[r11]
0xfb 0x07
+# CHECK: set dp, r5
+0xe5 0x37
+
+# CHECK: set cp, r0
+0xf0 0x37
+
+# CHECK: dgetreg r11
+0xeb 0x3f
+
+# CHECK: edu res[r8]
+0xe8 0x07
+
+# CHECK: kcall r2
+0xe2 0x47
+
+# CHECK: waitef r10
+0xfa 0x0f
+
+# CHECK: waitet r7
+0xe7 0x0f
+
+# CHECK: start t[r4]
+0xe4 0x1f
+
+# CHECK: clrpt res[r9]
+0xe9 0x87
+
# 2r instructions
# CHECK: not r1, r8