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| author | Chris Lattner <sabre@nondot.org> | 2006-03-24 07:12:19 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-03-24 07:12:19 +0000 |
| commit | 9d5da1d96cc90cc04a57c1cb1aa6f47e6bb99ef7 (patch) | |
| tree | bf5fc01a2df6c89d7e6fe0f724ac3a4c34fa1b92 | |
| parent | 9a0c9551fabcb032b446ac97ede00c87c25cb6a4 (diff) | |
| download | external_llvm-9d5da1d96cc90cc04a57c1cb1aa6f47e6bb99ef7.zip external_llvm-9d5da1d96cc90cc04a57c1cb1aa6f47e6bb99ef7.tar.gz external_llvm-9d5da1d96cc90cc04a57c1cb1aa6f47e6bb99ef7.tar.bz2 | |
Gabor points out that we can't spell. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27049 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/X86/README.txt | 4 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index fe9740f..b177237 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -659,7 +659,7 @@ def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB), /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending. /// /// Note that these are defined as pseudo-ops on the PPC970 because they are -/// often coallesced away and we don't want the dispatch group builder to think +/// often coalesced away and we don't want the dispatch group builder to think /// that they will fill slots (which could cause the load of a LSU reject to /// sneak into a d-group with a store). def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB), diff --git a/lib/Target/X86/README.txt b/lib/Target/X86/README.txt index 0cf645c..91bdb53 100644 --- a/lib/Target/X86/README.txt +++ b/lib/Target/X86/README.txt @@ -547,7 +547,7 @@ feasible. //===---------------------------------------------------------------------===// -Teach the coallescer to commute 2-addr instructions, allowing us to eliminate +Teach the coalescer to commute 2-addr instructions, allowing us to eliminate the reg-reg copy in this example: float foo(int *x, float *y, unsigned c) { @@ -642,7 +642,7 @@ lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor. //===---------------------------------------------------------------------===// -Teach the coallescer to coales vregs of different register classes. e.g. FR32 / +Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 / FR64 to VR128. //===---------------------------------------------------------------------===// diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 540fc11..5649d64 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -660,10 +660,10 @@ static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, // EDX". Anything more is illegal. // // FIXME: The linscan register allocator currently has problem with -// coallescing. At the time of this writing, whenever it decides to coallesce +// coalescing. At the time of this writing, whenever it decides to coalesce // a physreg with a virtreg, this increases the size of the physreg's live // range, and the live range cannot ever be reduced. This causes problems if -// too many physregs are coalleced with virtregs, which can cause the register +// too many physregs are coaleced with virtregs, which can cause the register // allocator to wedge itself. // // This code triggers this problem more often if we pass args in registers, |