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authorEric Christopher <echristo@apple.com>2012-07-02 21:16:43 +0000
committerEric Christopher <echristo@apple.com>2012-07-02 21:16:43 +0000
commit9eb4f8a3e665e0fe37509e632b97877b29b3c106 (patch)
treea05a19e8041e0219d299bc64c2cffd5bbc5eea3f
parente45658cc3c47d21140ee8680fb22bf664a996fbd (diff)
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Turn an assert into an error to make it a bit more friendly.
Part of rdar://6880388 and rdar://11766377 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159590 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp11
1 files changed, 9 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 72e5769..4fd95e9 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -6250,8 +6250,15 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
OpInfo.ConstraintType == TargetLowering::C_Register) &&
"Unknown constraint type!");
- assert(!OpInfo.isIndirect &&
- "Don't know how to handle indirect register inputs yet!");
+
+ // TODO: Support this.
+ if (OpInfo.isIndirect) {
+ LLVMContext &Ctx = *DAG.getContext();
+ Ctx.emitError(CS.getInstruction(),
+ "Don't know how to handle indirect register inputs yet "
+ "for constraint '" + Twine(OpInfo.ConstraintCode) + "'");
+ break;
+ }
// Copy the input into the appropriate registers.
if (OpInfo.AssignedRegs.Regs.empty()) {