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author | Andrew Trick <atrick@apple.com> | 2011-03-04 02:03:45 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2011-03-04 02:03:45 +0000 |
commit | a0807f57caed954545661c23607c507f8d5c3d64 (patch) | |
tree | 383945cfdada7a6aae1af123d939937099a69d47 | |
parent | 566bd12e54247b96823112e945e67ed7b9b7dce0 (diff) | |
download | external_llvm-a0807f57caed954545661c23607c507f8d5c3d64.zip external_llvm-a0807f57caed954545661c23607c507f8d5c3d64.tar.gz external_llvm-a0807f57caed954545661c23607c507f8d5c3d64.tar.bz2 |
Minor pre-RA-sched fixes and cleanup.
Fix the PendingQueue, then disable it because it's not required for
the current schedulers' heuristics.
Fix the logic for the unused list-ilp scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126981 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 0b548b2..d253b31 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -295,7 +295,7 @@ void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { if (Height < MinAvailableCycle) MinAvailableCycle = Height; - if (isReady(SU)) { + if (isReady(PredSU)) { AvailableQueue->push(PredSU); } // CapturePred and others may have left the node in the pending queue, avoid @@ -502,6 +502,12 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) { AvailableQueue->ScheduledNode(SU); + // If HazardRec is disabled, count each inst as one cycle. + // Advance CurCycle before ReleasePredecessors to avoid useles pushed to + // PendingQueue for schedulers that implement HasReadyFilter. + if (!HazardRec->isEnabled()) + AdvanceToCycle(CurCycle + 1); + // Update liveness of predecessors before successors to avoid treating a // two-address node as a live range def. ReleasePredecessors(SU); @@ -524,8 +530,10 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) { // (1) No available instructions // (2) All pipelines full, so available instructions must have hazards. // - // If HazardRec is disabled, count each inst as one cycle. - if (!HazardRec->isEnabled() || HazardRec->atIssueLimit() + // If HazardRec is disabled, the cycle was advanced earlier. + // + // Check AvailableQueue after ReleasePredecessors in case of zero latency. + if ((HazardRec->isEnabled() && HazardRec->atIssueLimit()) || AvailableQueue->empty()) AdvanceToCycle(CurCycle + 1); } @@ -1318,7 +1326,7 @@ struct src_ls_rr_sort : public queue_sort { struct hybrid_ls_rr_sort : public queue_sort { enum { IsBottomUp = true, - HasReadyFilter = true + HasReadyFilter = false }; RegReductionPQBase *SPQ; @@ -1337,7 +1345,7 @@ struct hybrid_ls_rr_sort : public queue_sort { struct ilp_ls_rr_sort : public queue_sort { enum { IsBottomUp = true, - HasReadyFilter = true + HasReadyFilter = false }; RegReductionPQBase *SPQ; @@ -2112,7 +2120,7 @@ bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { != ScheduleHazardRecognizer::NoHazard) return false; - return SU->getHeight() <= CurCycle; + return true; } bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { @@ -2134,7 +2142,7 @@ bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { if (left->NumPreds > right->NumPreds) return false; else if (left->NumPreds < right->NumPreds) - return false; + return true; } return BURRSort(left, right, SPQ); |