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| author | Jim Grosbach <grosbach@apple.com> | 2012-04-10 17:31:55 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2012-04-10 17:31:55 +0000 |
| commit | a23ecc2ba945c9685a76552276e5f6f41859b4ab (patch) | |
| tree | 56d22b3af91aafccb0e3a87a56480236df1420d3 | |
| parent | 2330636a667b6015c038f2847139c9a5b3ee70ed (diff) | |
| download | external_llvm-a23ecc2ba945c9685a76552276e5f6f41859b4ab.zip external_llvm-a23ecc2ba945c9685a76552276e5f6f41859b4ab.tar.gz external_llvm-a23ecc2ba945c9685a76552276e5f6f41859b4ab.tar.bz2 | |
ARM fix cc_out operand handling for t2SUBrr instructions.
We were incorrectly conflating some add variants which don't have a
cc_out operand with the mirroring sub encodings, which do. Part of the
awesome non-orthogonality legacy of thumb1. Similarly, handling of
add/sub of an immediate was sometimes incorrectly removing the cc_out
operand for add/sub register variants.
rdar://11216577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154411 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 3 | ||||
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 7 | ||||
| -rw-r--r-- | test/MC/ARM/basic-thumb2-instructions.s | 12 |
3 files changed, 19 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 424c932..0385229 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -3984,13 +3984,14 @@ def : t2InstAlias<"sub${s}${p} $Rdn, $imm", (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; def : t2InstAlias<"sub${p} $Rdn, $imm", (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>; +def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm", + (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; def : t2InstAlias<"sub${s}${p} $Rdn, $Rm", (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm", (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>; - // Alias for compares without the ".w" optional width specifier. def : t2InstAlias<"cmn${p} $Rn, $Rm", (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index e9164bc..34dadf8 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -4770,7 +4770,7 @@ bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, static_cast<ARMOperand*>(Operands[4])->isReg() && static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && - (static_cast<ARMOperand*>(Operands[5])->isReg() || + ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) || static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) return true; // For Thumb2, add/sub immediate does not have a cc_out operand for the @@ -4854,7 +4854,10 @@ bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, (Operands.size() == 5 || Operands.size() == 6) && static_cast<ARMOperand*>(Operands[3])->isReg() && static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && - static_cast<ARMOperand*>(Operands[1])->getReg() == 0) + static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && + (static_cast<ARMOperand*>(Operands[4])->isImm() || + (Operands.size() == 6 && + static_cast<ARMOperand*>(Operands[5])->isImm()))) return true; return false; diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index c6ef8af..d2e208b 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -2686,6 +2686,12 @@ _func: sub r4, r5, r6, asr #5 sub r4, r5, r6, ror #5 sub.w r5, r2, r12, rrx + sub r2, sp, ip + sub sp, sp, ip + sub sp, ip + sub.w r2, sp, ip + sub.w sp, sp, ip + sub.w sp, ip @ CHECK: sub.w r4, r5, r6 @ encoding: [0xa5,0xeb,0x06,0x04] @ CHECK: sub.w r4, r5, r6, lsl #5 @ encoding: [0xa5,0xeb,0x46,0x14] @@ -2694,6 +2700,12 @@ _func: @ CHECK: sub.w r4, r5, r6, asr #5 @ encoding: [0xa5,0xeb,0x66,0x14] @ CHECK: sub.w r4, r5, r6, ror #5 @ encoding: [0xa5,0xeb,0x76,0x14] @ CHECK: sub.w r5, r2, r12, rrx @ encoding: [0xa2,0xeb,0x3c,0x05] +@ CHECK: sub.w r2, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x02] +@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d] +@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d] +@ CHECK: sub.w r2, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x02] +@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d] +@ CHECK: sub.w sp, sp, r12 @ encoding: [0xad,0xeb,0x0c,0x0d] @------------------------------------------------------------------------------ |