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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-09-07 17:34:15 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-09-07 17:34:15 +0000 |
| commit | a7390fadbaa8da49649d76786555c93bcb680de6 (patch) | |
| tree | d37d65e6406b675045cdbd6f9c5c1ea504e8dcb3 | |
| parent | 39646d96e76aea5d20bffb386233a0dbb5932a21 (diff) | |
| download | external_llvm-a7390fadbaa8da49649d76786555c93bcb680de6.zip external_llvm-a7390fadbaa8da49649d76786555c93bcb680de6.tar.gz external_llvm-a7390fadbaa8da49649d76786555c93bcb680de6.tar.bz2 | |
Custom DAGCombine for and/or/xor are for all ARMs.
The 'select' transformations apply to all ARM architectures and don't
require hasV6T2Ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163396 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 5f3a9c7..29ca8ea 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -796,12 +796,9 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) setTargetDAGCombine(ISD::ADD); setTargetDAGCombine(ISD::SUB); setTargetDAGCombine(ISD::MUL); - - if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) { - setTargetDAGCombine(ISD::AND); - setTargetDAGCombine(ISD::OR); - setTargetDAGCombine(ISD::XOR); - } + setTargetDAGCombine(ISD::AND); + setTargetDAGCombine(ISD::OR); + setTargetDAGCombine(ISD::XOR); if (Subtarget->hasV6Ops()) setTargetDAGCombine(ISD::SRL); |