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author | Tim Northover <Tim.Northover@arm.com> | 2013-01-31 20:46:53 +0000 |
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committer | Tim Northover <Tim.Northover@arm.com> | 2013-01-31 20:46:53 +0000 |
commit | a9da5c50e246966c04784756e2083dbfe606c448 (patch) | |
tree | 3455f123e7d2d9366585eb8a668b633cefcd67ac | |
parent | 2d95e43fd877f81f419485baed3bd559de55e4c4 (diff) | |
download | external_llvm-a9da5c50e246966c04784756e2083dbfe606c448.zip external_llvm-a9da5c50e246966c04784756e2083dbfe606c448.tar.gz external_llvm-a9da5c50e246966c04784756e2083dbfe606c448.tar.bz2 |
Update AArch64 backend to changed eliminateFrameIndex interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174086 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/AArch64/AArch64RegisterInfo.cpp | 22 | ||||
-rw-r--r-- | lib/Target/AArch64/AArch64RegisterInfo.h | 1 |
2 files changed, 10 insertions, 13 deletions
diff --git a/lib/Target/AArch64/AArch64RegisterInfo.cpp b/lib/Target/AArch64/AArch64RegisterInfo.cpp index ce66504..2481176 100644 --- a/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ b/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -78,7 +78,9 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const { void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MBBI, - int SPAdj, RegScavenger *RS) const { + int SPAdj, + unsigned FIOperandNum, + RegScavenger *RS) const { assert(SPAdj == 0 && "Cannot deal with nonzero SPAdj yet"); MachineInstr &MI = *MBBI; MachineBasicBlock &MBB = *MI.getParent(); @@ -87,12 +89,6 @@ AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MBBI, const AArch64FrameLowering *TFI = static_cast<const AArch64FrameLowering *>(MF.getTarget().getFrameLowering()); - unsigned i = 0; - while (!MI.getOperand(i).isFI()) { - ++i; - assert(i < MI.getNumOperands() && "Instr doesn't have a FrameIndex Operand"); - } - // In order to work out the base and offset for addressing, the FrameLowering // code needs to know (sometimes) whether the instruction is storing/loading a // callee-saved register, or whether it's a more generic @@ -107,7 +103,7 @@ AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MBBI, MaxCSFI = CSI[CSI.size() - 1].getFrameIdx(); } - int FrameIndex = MI.getOperand(i).getIndex(); + int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); bool IsCalleeSaveOp = FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI; unsigned FrameReg; @@ -115,13 +111,13 @@ AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MBBI, Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj, IsCalleeSaveOp); - Offset += MI.getOperand(i+1).getImm(); + Offset += MI.getOperand(FIOperandNum + 1).getImm(); // DBG_VALUE instructions have no real restrictions so they can be handled // easily. if (MI.isDebugValue()) { - MI.getOperand(i).ChangeToRegister(FrameReg, /*isDef=*/ false); - MI.getOperand(i+1).ChangeToImmediate(Offset); + MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/ false); + MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); return; } @@ -151,8 +147,8 @@ AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MBBI, // now this checks nothing has gone horribly wrong. assert(Offset >= 0 && "Unexpected negative offset from SP"); - MI.getOperand(i).ChangeToRegister(FrameReg, false, false, true); - MI.getOperand(i+1).ChangeToImmediate(Offset / OffsetScale); + MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, true); + MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset / OffsetScale); } void diff --git a/lib/Target/AArch64/AArch64RegisterInfo.h b/lib/Target/AArch64/AArch64RegisterInfo.h index ea538e2..3be083d 100644 --- a/lib/Target/AArch64/AArch64RegisterInfo.h +++ b/lib/Target/AArch64/AArch64RegisterInfo.h @@ -41,6 +41,7 @@ public: unsigned getFrameRegister(const MachineFunction &MF) const; void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, + unsigned FIOperandNum, RegScavenger *Rs = NULL) const; void eliminateCallFramePseudoInstr(MachineFunction &MF, |