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authorEvan Cheng <evan.cheng@apple.com>2008-09-25 00:14:04 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-09-25 00:14:04 +0000
commitaa765b8c35aa3a5cca9681d6e3c44091d94f23d9 (patch)
tree2f0a1d588b76ba79560a39ae0cf688c71fc2ab86
parentbd0f144cc2549e8c2f853ea0a914abd0aa29444f (diff)
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<rdar://problem/6234798> Assertion failed: (!OpInfo.AssignedRegs.Regs.empty() && "Couldn't allocate input reg!")
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56597 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp7
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 1365d68..ac4a639 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -4940,8 +4940,11 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
"Don't know how to handle indirect register inputs yet!");
// Copy the input into the appropriate registers.
- assert(!OpInfo.AssignedRegs.Regs.empty() &&
- "Couldn't allocate input reg!");
+ if (OpInfo.AssignedRegs.Regs.empty()) {
+ cerr << "Couldn't allocate output reg for constraint '"
+ << OpInfo.ConstraintCode << "'!\n";
+ exit(1);
+ }
OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);