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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-20 18:20:31 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-20 18:20:31 +0000 |
| commit | ab40f4b737b0a87c4048a9ad2f0c02be735e3770 (patch) | |
| tree | 5acd32e18f438a76dcaf72589d2198d7f799ce18 | |
| parent | 0381c21d2ddc182aebfef25c6500d781ddb428fe (diff) | |
| download | external_llvm-ab40f4b737b0a87c4048a9ad2f0c02be735e3770.zip external_llvm-ab40f4b737b0a87c4048a9ad2f0c02be735e3770.tar.gz external_llvm-ab40f4b737b0a87c4048a9ad2f0c02be735e3770.tar.bz2 | |
ARM assembly parsing of MUL instruction.
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 3 | ||||
| -rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 14 |
2 files changed, 16 insertions, 1 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 0cf9a4a..89501dc 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -1977,7 +1977,8 @@ StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic, // First, split out any predication code. Ignore mnemonics we know aren't // predicated but do have a carry-set and so weren't caught above. - if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs") { + if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && + Mnemonic != "muls") { unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) .Case("eq", ARMCC::EQ) .Case("ne", ARMCC::NE) diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 00cfec9..9fb90d2 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -812,6 +812,20 @@ _func: @ CHECK: msr CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1] @------------------------------------------------------------------------------ +@ MUL +@------------------------------------------------------------------------------ + + mul r5, r6, r7 + muls r5, r6, r7 + mulgt r5, r6, r7 + mulsle r5, r6, r7 + +@ CHECK: mul r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xe0] +@ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0] +@ CHECK: mulgt r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xc0] +@ CHECK: mulsle r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xd0] + +@------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------ stm r2, {r1,r3-r6,sp} |