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author | Dan Gohman <gohman@apple.com> | 2009-12-07 19:04:31 +0000 |
---|---|---|
committer | Dan Gohman <gohman@apple.com> | 2009-12-07 19:04:31 +0000 |
commit | ad1cc9c85c6ebd136855b133cfa0397741c2dcbf (patch) | |
tree | bbb0b0631c9249f9a93fc21acdc7d5470b009031 | |
parent | a3fce13cb0bd4c4afcf1c28f788a398df6a560dc (diff) | |
download | external_llvm-ad1cc9c85c6ebd136855b133cfa0397741c2dcbf.zip external_llvm-ad1cc9c85c6ebd136855b133cfa0397741c2dcbf.tar.gz external_llvm-ad1cc9c85c6ebd136855b133cfa0397741c2dcbf.tar.bz2 |
Don't enable the post-RA scheduler on x86 except at -O3. In its
current form, it is too expensive in compile time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90781 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/X86/X86Subtarget.cpp | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/2007-01-08-InstrSched.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/sink-hoist.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/sse2.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/sse3.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/tail-opts.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/tailcallstack64.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/widen_arith-3.ll | 2 |
9 files changed, 9 insertions, 9 deletions
diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp index 661f560..75cdbad 100644 --- a/lib/Target/X86/X86Subtarget.cpp +++ b/lib/Target/X86/X86Subtarget.cpp @@ -367,5 +367,5 @@ bool X86Subtarget::enablePostRAScheduler( RegClassVector& CriticalPathRCs) const { Mode = TargetSubtarget::ANTIDEP_CRITICAL; CriticalPathRCs.clear(); - return OptLevel >= CodeGenOpt::Default; + return OptLevel >= CodeGenOpt::Aggressive; } diff --git a/test/CodeGen/X86/2007-01-08-InstrSched.ll b/test/CodeGen/X86/2007-01-08-InstrSched.ll index 81f0a1d..317ed0a 100644 --- a/test/CodeGen/X86/2007-01-08-InstrSched.ll +++ b/test/CodeGen/X86/2007-01-08-InstrSched.ll @@ -1,5 +1,5 @@ ; PR1075 -; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -O3 | FileCheck %s define float @foo(float %x) nounwind { %tmp1 = fmul float %x, 3.000000e+00 diff --git a/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll b/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll index d372da3..8cb538b 100644 --- a/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll +++ b/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-darwin10 -post-RA-scheduler=true | FileCheck %s ; PR4958 diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll index f8d542e..01d7373 100644 --- a/test/CodeGen/X86/sink-hoist.ll +++ b/test/CodeGen/X86/sink-hoist.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu | FileCheck %s +; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu -post-RA-scheduler=true | FileCheck %s ; Currently, floating-point selects are lowered to CFG triangles. ; This means that one side of the select is always unconditionally diff --git a/test/CodeGen/X86/sse2.ll b/test/CodeGen/X86/sse2.ll index 58fe28b..f2b8010 100644 --- a/test/CodeGen/X86/sse2.ll +++ b/test/CodeGen/X86/sse2.ll @@ -1,5 +1,5 @@ ; Tests for SSE2 and below, without SSE3+. -; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=pentium4 | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=pentium4 -O3 | FileCheck %s define void @t1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind { %tmp3 = load <2 x double>* %A, align 16 diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll index 21c1a3c..5550d26 100644 --- a/test/CodeGen/X86/sse3.ll +++ b/test/CodeGen/X86/sse3.ll @@ -1,6 +1,6 @@ ; These are tests for SSE3 codegen. Yonah has SSE3 and earlier but not SSSE3+. -; RUN: llc < %s -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9\ +; RUN: llc < %s -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9 -O3 \ ; RUN: | FileCheck %s --check-prefix=X64 ; Test for v8xi16 lowering where we extract the first element of the vector and diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll index 0d86e56..c70c9fa 100644 --- a/test/CodeGen/X86/tail-opts.ll +++ b/test/CodeGen/X86/tail-opts.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false | FileCheck %s +; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false -post-RA-scheduler=true | FileCheck %s declare void @bar(i32) declare void @car(i32) diff --git a/test/CodeGen/X86/tailcallstack64.ll b/test/CodeGen/X86/tailcallstack64.ll index 69018aa..d05dff8 100644 --- a/test/CodeGen/X86/tailcallstack64.ll +++ b/test/CodeGen/X86/tailcallstack64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -tailcallopt -march=x86-64 | FileCheck %s +; RUN: llc < %s -tailcallopt -march=x86-64 -post-RA-scheduler=true | FileCheck %s ; Check that lowered arguments on the stack do not overwrite each other. ; Add %in1 %p1 to a different temporary register (%eax). diff --git a/test/CodeGen/X86/widen_arith-3.ll b/test/CodeGen/X86/widen_arith-3.ll index a2b8b82..1f2c250 100644 --- a/test/CodeGen/X86/widen_arith-3.ll +++ b/test/CodeGen/X86/widen_arith-3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -post-RA-scheduler=true | FileCheck %s ; CHECK: paddw ; CHECK: pextrw ; CHECK: movd |