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| author | Bill Wendling <isanbard@gmail.com> | 2013-11-21 07:07:01 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2013-11-21 07:07:01 +0000 |
| commit | ade90c9f1d01f3401a5db183a33b5a6380476a35 (patch) | |
| tree | e1330ada0e63b3000a6aa6c7f44ed3efd47f902f | |
| parent | 8ae03404a3a38e34474d29f20bf5cd6b7088ada8 (diff) | |
| download | external_llvm-ade90c9f1d01f3401a5db183a33b5a6380476a35.zip external_llvm-ade90c9f1d01f3401a5db183a33b5a6380476a35.tar.gz external_llvm-ade90c9f1d01f3401a5db183a33b5a6380476a35.tar.bz2 | |
Merging r195272:
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r195272 | hfinkel | 2013-11-20 12:54:55 -0800 (Wed, 20 Nov 2013) | 4 lines
PPC popcnt[dw] do not have record forms
The instruction definitions incorrectly specified that popcntd and popcntw have
record forms; they do not. This mistake was causing invalid code generation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195320 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCInstr64Bit.td | 12 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/optcmp.ll | 16 |
2 files changed, 22 insertions, 6 deletions
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index 46aafbe..46db4fe 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -529,16 +529,16 @@ defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), "cntlzd", "$rA, $rS", IntGeneral, [(set i64:$rA, (ctlz i64:$rS))]>; -defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), - "popcntd", "$rA, $rS", IntGeneral, - [(set i64:$rA, (ctpop i64:$rS))]>; +def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), + "popcntd $rA, $rS", IntGeneral, + [(set i64:$rA, (ctpop i64:$rS))]>; // popcntw also does a population count on the high 32 bits (storing the // results in the high 32-bits of the output). We'll ignore that here (which is // safe because we never separately use the high part of the 64-bit registers). -defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS), - "popcntw", "$rA, $rS", IntGeneral, - [(set i32:$rA, (ctpop i32:$rS))]>; +def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), + "popcntw $rA, $rS", IntGeneral, + [(set i32:$rA, (ctpop i32:$rS))]>; defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), "divd", "$rT, $rA, $rB", IntDivD, diff --git a/test/CodeGen/PowerPC/optcmp.ll b/test/CodeGen/PowerPC/optcmp.ll index c2cf981..35aabfa 100644 --- a/test/CodeGen/PowerPC/optcmp.ll +++ b/test/CodeGen/PowerPC/optcmp.ll @@ -134,3 +134,19 @@ entry: ; CHECK-NOT: fsubs. 0, 1, 2 ; CHECK: stfs 0, 0(5) } + +declare i64 @llvm.ctpop.i64(i64); + +define signext i64 @fooct(i64 signext %a, i64 signext %b, i64* nocapture %c) #0 { +entry: + %sub = sub nsw i64 %a, %b + %subc = call i64 @llvm.ctpop.i64(i64 %sub) + store i64 %subc, i64* %c, align 4 + %cmp = icmp sgt i64 %subc, 0 + %cond = select i1 %cmp, i64 %a, i64 %b + ret i64 %cond + +; CHECK: @fooct +; CHECK-NOT: popcntd. +} + |